41 lines
656 B
Makefile
41 lines
656 B
Makefile
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# Compiler
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CC := gcc
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# Compiler flags
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CFLAGS := -Wall -Wextra -Wpedantic
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# Directories
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SRC_DIR := src
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BUILD_DIR := build
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# Source files
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SRCS := $(wildcard $(SRC_DIR)/*.c)
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# Object files
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OBJS := $(patsubst $(SRC_DIR)/%.c,$(BUILD_DIR)/%.o,$(SRCS))
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# Target executable
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TARGET := CTree
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# Default target
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all: $(TARGET)
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# Rule to build the target executable
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$(TARGET): $(OBJS)
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$(CC) $(CFLAGS) $^ -o $@
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# Rule to build object files
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$(BUILD_DIR)/%.o: $(SRC_DIR)/%.c
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@mkdir -p $(BUILD_DIR)
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$(CC) $(CFLAGS) -c $< -o $@
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# Run rule
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run: $(TARGET)
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./$(TARGET)
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# Clean rule
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clean:
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rm -rf $(BUILD_DIR) $(TARGET)
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# Mark rules as phony
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.PHONY: all run clean
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