Risc-V-Asm/link.ld

MEMORY {
    SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 1024
    DRAM (rwx) : ORIGIN = 0x80000000, LENGTH = 1024
}

SECTIONS {
    .text : {
        main.o(.text.*)
        *(.text)
    } > DRAM
    .data : {
        *(.data)
    } > DRAM AT > SRAM
    .bss : {
        *(.bss)
    } > DRAM
    /DISCARD/ : {
        *(.riscv.attributes)
    }
}