Risc-V-Asm/link.ld

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2024-04-05 17:04:19 +02:00
MEMORY {
SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 1024
DRAM (rwx) : ORIGIN = 0x80000000, LENGTH = 1024
}
SECTIONS {
.text : {
*(.text)
} > SRAM
.data : {
*(.data)
} > DRAM AT > SRAM
.bss : {
*(.bss)
} > DRAM
}