Imbus/Risc-V-Asm
1
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

Square

Browse source
This commit is contained in:
Imbus 2024-12-09 12:25:56 +01:00
parent 1a31859a31
commit b65b33da25
5 changed files with 20 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
Makefile
View file

@ -24,6 +24,7 @@ CFLAGS += -fno-common# # Do not use common sections
CFLAGS += -march=rv64i# # Use RV64I ISA, i.e., integer only CFLAGS += -march=rv64i# # Use RV64I ISA, i.e., integer only
CFLAGS += -mabi=lp64# # Use LP64 ABI, i.e., 64-bit longs and pointers, 32-bit ints CFLAGS += -mabi=lp64# # Use LP64 ABI, i.e., 64-bit longs and pointers, 32-bit ints
CFLAGS += -Os# # Optimize for size CFLAGS += -Os# # Optimize for size
CFLAGS += -Wall -Wunused -O2
LDFLAGS += -T link.ld # Use the linker script LDFLAGS += -T link.ld # Use the linker script
LDFLAGS += --no-dynamic-linker LDFLAGS += --no-dynamic-linker

2
link.ld
View file

@ -5,7 +5,7 @@ MEMORY {
SECTIONS { SECTIONS {
.text : { .text : {
main.o(.text.*) *(.text)
*(.text) *(.text)
. = ALIGN(4); . = ALIGN(4);
} > DRAM } > DRAM

1
square.h Normal file
View file

@ -0,0 +1 @@
int square(int, int);

15
square.s Normal file
View file

@ -0,0 +1,15 @@
square:
addi sp,sp,-32
sd ra,24(sp)
sd s0,16(sp)
addi s0,sp,32
mv a5,a0
sw a5,-20(s0)
lw a5,-20(s0)
mulw a5,a5,a5
sext.w a5,a5
mv a0,a5
ld ra,24(sp)
ld s0,16(sp)
addi sp,sp,32
jr ra