From 1e041aadfbddb936a029e4cf9d42fd834c10ebf8 Mon Sep 17 00:00:00 2001
From: Imbus <>
Date: Sat, 6 Apr 2024 21:20:29 +0200
Subject: [PATCH 1/3] Makefile for clearer disassembly and a sections target

---
 makefile | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/makefile b/makefile
index 105c032..9d21460 100644
--- a/makefile
+++ b/makefile
@@ -67,7 +67,10 @@ run: all
 
 # View the text section of the binary
 inspect: all
-	$(OBJDUMP) -d $(TARGET)
+	$(OBJDUMP) -dC $(TARGET)
+
+sections: all
+	$(OBJDUMP) -h $(TARGET)
 
 # View the disassembly
 raw: all

From 7efabe6a31564828e931c357beb04e532b5cd5ef Mon Sep 17 00:00:00 2001
From: Imbus <>
Date: Sat, 6 Apr 2024 21:20:45 +0200
Subject: [PATCH 2/3] Discard metadata section in linker script

---
 link.ld | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/link.ld b/link.ld
index c5a85b0..8401657 100644
--- a/link.ld
+++ b/link.ld
@@ -14,4 +14,7 @@ SECTIONS {
     .bss : {
         *(.bss)
     } > DRAM
+    /DISCARD/ : {
+        *(.riscv.attributes)
+    }
 }

From 3725cbe58d64fffc3ca785bfda1a64ff450f5caa Mon Sep 17 00:00:00 2001
From: Imbus <>
Date: Sat, 6 Apr 2024 21:20:53 +0200
Subject: [PATCH 3/3] More resources

---
 README.md | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/README.md b/README.md
index 8aa796c..eaff1d7 100644
--- a/README.md
+++ b/README.md
@@ -6,6 +6,7 @@
 - [RISC-V Greehsheet](https://raw.githubusercontent.com/rswinkle/riscv_book/master/references/riscv_greensheet.pdf) and its [large version](https://raw.githubusercontent.com/rswinkle/riscv_book/master/references/riscv_greensheet_large.pdf)
 - [RISC-V ISA Manual](https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf)
 - [RISC-V Specifications](https://riscv.org/technical/specifications/)
+- [RISC-V Assembler Reference](https://michaeljclark.github.io/asm.html)
 
 ### Misc
 
@@ -15,3 +16,8 @@
   - [RISC-V from scratch 3: Writing a UART driver in assembly](https://twilco.github.io/riscv-from-scratch/2019/07/08/riscv-from-scratch-3.html)
   - [RISC-V from scratch 4: Creating a function prologue for our UART driver](https://twilco.github.io/riscv-from-scratch/2019/07/28/riscv-from-scratch-4.html)
 - [RISC-V Assembly Language Programming](https://github.com/rswinkle/riscv_book/)
+- [CNLohr's RISC-V emulator](https://github.com/cnlohr/mini-rv32ima/tree/master)
+
+### More Misc
+
+- [How to Run Linux on RISC-V with QEMU Emulator](https://www.cnx-software.com/2018/03/16/how-to-run-linux-on-risc-v-with-qemu-emulator)