More resources

README.md

@@ -6,6 +6,7 @@
 - [RISC-V Greehsheet](https://raw.githubusercontent.com/rswinkle/riscv_book/master/references/riscv_greensheet.pdf) and its [large version](https://raw.githubusercontent.com/rswinkle/riscv_book/master/references/riscv_greensheet_large.pdf)
 - [RISC-V ISA Manual](https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf)
 - [RISC-V Specifications](https://riscv.org/technical/specifications/)
+- [RISC-V Assembler Reference](https://michaeljclark.github.io/asm.html)
 
 ### Misc
 
@@ -15,3 +16,8 @@
   - [RISC-V from scratch 3: Writing a UART driver in assembly](https://twilco.github.io/riscv-from-scratch/2019/07/08/riscv-from-scratch-3.html)
   - [RISC-V from scratch 4: Creating a function prologue for our UART driver](https://twilco.github.io/riscv-from-scratch/2019/07/28/riscv-from-scratch-4.html)
 - [RISC-V Assembly Language Programming](https://github.com/rswinkle/riscv_book/)
+- [CNLohr's RISC-V emulator](https://github.com/cnlohr/mini-rv32ima/tree/master)
+
+### More Misc
+
+- [How to Run Linux on RISC-V with QEMU Emulator](https://www.cnx-software.com/2018/03/16/how-to-run-linux-on-risc-v-with-qemu-emulator)

link.ld

@@ -14,4 +14,7 @@ SECTIONS {
     .bss : {
         *(.bss)
     } > DRAM
+    /DISCARD/ : {
+        *(.riscv.attributes)
+    }
 }

makefile

@@ -67,7 +67,10 @@ run: all
 
 # View the text section of the binary
 inspect: all
-	$(OBJDUMP) -d $(TARGET)
+	$(OBJDUMP) -dC $(TARGET)
+
+sections: all
+	$(OBJDUMP) -h $(TARGET)
 
 # View the disassembly
 raw: all