Risc-V-Asm/link.ld
2024-12-09 12:25:56 +01:00

23 lines
405 B
Text

MEMORY {
SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 1024
DRAM (rwx) : ORIGIN = 0x80000000, LENGTH = 1024
}
SECTIONS {
.text : {
*(.text)
*(.text)
. = ALIGN(4);
} > DRAM
.data : {
*(.data)
. = ALIGN(4);
} > DRAM AT > SRAM
.bss : {
*(.bss)
. = ALIGN(4);
} > DRAM
/DISCARD/ : {
*(.riscv.attributes)
}
}