Risc-V-Asm/link.ld
2024-04-07 14:56:53 +02:00

23 lines
412 B
Text

MEMORY {
SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 1024
DRAM (rwx) : ORIGIN = 0x80000000, LENGTH = 1024
}
SECTIONS {
.text : {
main.o(.text.*)
*(.text)
. = ALIGN(4);
} > DRAM
.data : {
*(.data)
. = ALIGN(4);
} > DRAM AT > SRAM
.bss : {
*(.bss)
. = ALIGN(4);
} > DRAM
/DISCARD/ : {
*(.riscv.attributes)
}
}