Verilog/blinky.v

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2024-04-01 10:40:00 +02:00
// blinky.v
// Blink the green LED with frequency 12e6/2^24 = 0.7Hz approx.
module top (clk_in, led_green_out);
input clk_in;
output led_green_out;
reg [23:0] counter;
assign led_green_out = counter[23];
assign led_red[3:0] = 4'b0;
always @ (posedge clk_in) begin
counter <= counter + 1;
end
endmodule