Makefile

makefile

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+# This is a standard makefile for building a kernel module.
+# It looks a bit backwards compared to a normal makefile, but that's because
+# the kernel supplies its own sub-makefile that we use to build the module.
+# 
+# The M= option tells the kernel's makefile where to find the module's source
+# files, and the -C option sets the context directory for make.
+#
+# The obj-m variable tells the kernel's makefile what the module's object file
+# should be called. In this case, it's demo_module.o. This is how the sub-makefile
+# infers the name of the module's source file.
+# 
+# This build is highly sensitive to compiler version, and requires the system gcc
+# to be the same version as the gcc that built the current kernel.
+
+obj-m = demo_module.o
+
+all:
+	make -C /lib/modules/$(shell uname -r)/build/ M=$(PWD) modules
+
+clean:
+	make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean