From 2aa06778b382cda2a6a764edd60348776509ddc2 Mon Sep 17 00:00:00 2001
From: Imbus <>
Date: Thu, 26 Jun 2025 13:30:45 +0200
Subject: [PATCH] riscv.h, start.c: Some changed and some new machine specific
 routines

---
 riscv.h | 80 +++++++++++++++++++++++++++++++++++++++++----------------
 start.c | 12 ++++++---
 2 files changed, 66 insertions(+), 26 deletions(-)

diff --git a/riscv.h b/riscv.h
index 91b17b0..3114b79 100644
--- a/riscv.h
+++ b/riscv.h
@@ -3,22 +3,20 @@
 
 #include <types.h>
 
+/** Page Size */
+#define PGSIZE 4096 // bytes per page
+
+// /** Page Shift, bits of offset within a page */
+#define PGSHIFT        12
+#define PGROUNDUP(sz)  (((sz) + PGSIZE - 1) & ~(PGSIZE - 1))
+#define PGROUNDDOWN(a) (((a)) & ~(PGSIZE - 1))
+
 // Supervisor Status Register, sstatus
-
-/** Supervisor Previous Privilege */
-#define SSTATUS_SPP (1L << 8) // Previous mode, 1=Supervisor, 0=User
-
-/** Supervisor Previous Interrupt Enable */
-#define SSTATUS_SPIE (1L << 5)
-
-/** User Previous Interrupt Enable */
-#define SSTATUS_UPIE (1L << 4)
-
-/** Supervisor Interrupt Enable */
-#define SSTATUS_SIE (1L << 1)
-
-/** User Interrupt Enable */
-#define SSTATUS_UIE (1L << 0)
+#define SSTATUS_SPP  (1L << 8) /** Supervisor Previous Privilege 1=S, 0=U */
+#define SSTATUS_SPIE (1L << 5) /** Supervisor Previous Interrupt Enable */
+#define SSTATUS_UPIE (1L << 4) /** User Previous Interrupt Enable */
+#define SSTATUS_SIE  (1L << 1) /** Supervisor Interrupt Enable */
+#define SSTATUS_UIE  (1L << 0) /** User Interrupt Enable */
 
 /** Page Table Entry Type */
 typedef u64 pte_t;
@@ -26,22 +24,60 @@ typedef u64 pte_t;
 /** Page Table Type */
 typedef u64 *pagetable_t; // 512 PTEs
 
-/** Returns the current hart id */
-static inline u64 r_mhartid() {
-    u64 x;
-    asm volatile("csrr %0, mhartid" : "=r"(x));
-    return x;
+// CSR numeric addresses
+#define CSR_MSTATUS    0x300
+#define CSR_MISA       0x301
+#define CSR_MIE        0x304
+#define CSR_MTVEC      0x305
+#define CSR_MCOUNTEREN 0x306
+
+#define CSR_MSCRATCH 0x340
+#define CSR_MEPC     0x341
+#define CSR_MCAUSE   0x342
+#define CSR_MTVAL    0x343
+#define CSR_MIP      0x344
+
+#define CSR_MHARTID 0xF14
+
+static inline u64 read_csr(u32 csr) {
+    u64 value;
+    asm volatile("csrr %0, %1" : "=r"(value) : "i"(csr));
+    return value;
 }
 
+static inline void write_csr(u32 csr, u64 value) {
+    asm volatile("csrw %0, %1" ::"i"(csr), "r"(value));
+}
+
+static inline u64  read_mstatus(void) { return read_csr(CSR_MSTATUS); }
+static inline void write_mstatus(u64 val) { write_csr(CSR_MSTATUS, val); }
+
+static inline u64  read_mcause(void) { return read_csr(CSR_MCAUSE); }
+static inline u64  read_mtval(void) { return read_csr(CSR_MTVAL); }
+static inline u64  read_mepc(void) { return read_csr(CSR_MEPC); }
+static inline void write_mepc(u64 val) { write_csr(CSR_MEPC, val); }
+
+static inline void write_mtvec(u64 val) { write_csr(CSR_MTVEC, val); }
+static inline u64  read_mtvec(void) { return read_csr(CSR_MTVEC); }
+
+/** Returns the current hart id */
+static inline u64 read_mhartid(void) { return read_csr(CSR_MHARTID); }
+
+// static inline u64 r_mhartid() {
+//     u64 x;
+//     asm volatile("csrr %0, mhartid" : "=r"(x));
+//     return x;
+// }
+
 /** Read thread pointer */
-static inline u64 r_tp() {
+static inline u64 read_tp() {
     u64 x;
     asm volatile("mv %0, tp" : "=r"(x));
     return x;
 }
 
 /** Write thread pointer */
-static inline void w_tp(u64 x) { asm volatile("mv tp, %0" : : "r"(x)); }
+static inline void write_tp(u64 x) { asm volatile("mv tp, %0" : : "r"(x)); }
 
 /**
  * Read the value of the sstatus register.
diff --git a/start.c b/start.c
index 8d369f9..d9ca8ef 100644
--- a/start.c
+++ b/start.c
@@ -1,8 +1,9 @@
 #include <config.h>
+#include <kalloc.h>
+#include <memory.h>
 #include <proc.h>
 #include <riscv.h>
 #include <spinlock.h>
-#include <string.h>
 #include <types.h>
 #include <uart.h>
 
@@ -20,13 +21,13 @@ volatile int    greeted = 0;
 
 /* This is where entry.S drops us of. All cores land here */
 void start() {
-    u64 id = r_mhartid();
+    u64 id = read_mhartid();
 
     // Keep each CPU's hartid in its tp (thread pointer) register, for cpuid().
     // This can then be retrieved with r_wp or cpuid(). It is used to index the
     // cpus[] array in mycpu(), which in turn holds state for each individual
     // cpu (struct Cpu).
-    w_tp(id);
+    write_tp(id);
 
     acquire(&sl);
 
@@ -41,7 +42,10 @@ void start() {
 
     release(&sl);
 
-    /* Here we will do a bunch of initialization steps */
+    if (id == 0) {
+        /* Here we will do a bunch of initialization steps */
+        kalloc_init();
+    }
 
     // We should not arrive here, but if we do, hang in a while on wfi.
     while (1) __asm__ volatile("wfi"); // (Wait For Interrupt)