Alias
This commit is contained in:
parent
13b91e7aae
commit
3f74e55322
3 changed files with 1 additions and 91 deletions
74
riscv.h
74
riscv.h
|
@ -1,74 +0,0 @@
|
||||||
#ifndef RISCV_KERNEL_H
|
|
||||||
#define RISCV_KERNEL_H
|
|
||||||
|
|
||||||
#include <types.h>
|
|
||||||
|
|
||||||
/** Page Size */
|
|
||||||
#define PGSIZE 4096 // bytes per page
|
|
||||||
|
|
||||||
// /** Page Shift, bits of offset within a page */
|
|
||||||
#define PGSHIFT 12
|
|
||||||
#define PGROUNDUP(sz) (((sz) + PGSIZE - 1) & ~(PGSIZE - 1))
|
|
||||||
#define PGROUNDDOWN(a) (((a)) & ~(PGSIZE - 1))
|
|
||||||
|
|
||||||
// Supervisor Status Register, sstatus
|
|
||||||
#define SSTATUS_SPP (1L << 8) /** Supervisor Previous Privilege 1=S, 0=U */
|
|
||||||
#define SSTATUS_SPIE (1L << 5) /** Supervisor Previous Interrupt Enable */
|
|
||||||
#define SSTATUS_UPIE (1L << 4) /** User Previous Interrupt Enable */
|
|
||||||
#define SSTATUS_SIE (1L << 1) /** Supervisor Interrupt Enable */
|
|
||||||
#define SSTATUS_UIE (1L << 0) /** User Interrupt Enable */
|
|
||||||
|
|
||||||
/** Page Table Entry Type */
|
|
||||||
typedef u64 pte_t;
|
|
||||||
|
|
||||||
/** Page Table Type */
|
|
||||||
typedef u64 *pagetable_t; // 512 PTEs
|
|
||||||
|
|
||||||
/** Returns the current hart id */
|
|
||||||
static inline u64 read_mhartid() {
|
|
||||||
u64 x;
|
|
||||||
asm volatile("csrr %0, mhartid" : "=r"(x));
|
|
||||||
return x;
|
|
||||||
}
|
|
||||||
|
|
||||||
/** Read thread pointer */
|
|
||||||
static inline u64 read_tp() {
|
|
||||||
u64 x;
|
|
||||||
asm volatile("mv %0, tp" : "=r"(x));
|
|
||||||
return x;
|
|
||||||
}
|
|
||||||
|
|
||||||
/** Write thread pointer */
|
|
||||||
static inline void write_tp(u64 x) { asm volatile("mv tp, %0" : : "r"(x)); }
|
|
||||||
|
|
||||||
/**
|
|
||||||
* Read the value of the sstatus register.
|
|
||||||
* (Supervisor Status Register)
|
|
||||||
*/
|
|
||||||
static inline u64 r_sstatus() {
|
|
||||||
u64 x;
|
|
||||||
asm volatile("csrr %0, sstatus" : "=r"(x));
|
|
||||||
return x;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* Write a value to the sstatus register.
|
|
||||||
* (Supervisor Status Register)
|
|
||||||
*/
|
|
||||||
static inline void w_sstatus(u64 x) {
|
|
||||||
asm volatile("csrw sstatus, %0" : : "r"(x));
|
|
||||||
}
|
|
||||||
|
|
||||||
/** Enable device interrupts */
|
|
||||||
static inline void intr_on() { w_sstatus(r_sstatus() | SSTATUS_SIE); }
|
|
||||||
|
|
||||||
/** Disable device interrupts */
|
|
||||||
static inline void intr_off() { w_sstatus(r_sstatus() & ~SSTATUS_SIE); }
|
|
||||||
|
|
||||||
/** Are device interrupts enabled? */
|
|
||||||
static inline int intr_get() {
|
|
||||||
u64 x = r_sstatus();
|
|
||||||
return (x & SSTATUS_SIE) != 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
|
2
start.c
2
start.c
|
@ -4,7 +4,7 @@
|
||||||
#include <memory.h>
|
#include <memory.h>
|
||||||
#include <proc.h>
|
#include <proc.h>
|
||||||
#include <riscv.h>
|
#include <riscv.h>
|
||||||
#include <types.h>
|
#include <stdint.h>
|
||||||
#include <uart.h>
|
#include <uart.h>
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
16
types.h
16
types.h
|
@ -1,16 +0,0 @@
|
||||||
#pragma once
|
|
||||||
|
|
||||||
typedef unsigned char u8;
|
|
||||||
typedef unsigned short u16;
|
|
||||||
typedef unsigned int u32;
|
|
||||||
typedef unsigned long u64;
|
|
||||||
|
|
||||||
typedef unsigned char uint8_t;
|
|
||||||
typedef unsigned short uint16_t;
|
|
||||||
typedef unsigned int uint32_t;
|
|
||||||
typedef unsigned long uint64_t;
|
|
||||||
typedef uint64_t size_t;
|
|
||||||
|
|
||||||
typedef uint64_t uintptr_t;
|
|
||||||
|
|
||||||
typedef u8 bool;
|
|
Loading…
Add table
Reference in a new issue