From 50a3c8d1d9ab2cd54905349280f1d994af432a93 Mon Sep 17 00:00:00 2001
From: Imbus <>
Date: Thu, 26 Jun 2025 04:21:51 +0200
Subject: [PATCH] riscv.h architecture specific routines, startcode now
 branches hartid=0 for initialziation and hangs the other cores

---
 riscv.h |  8 ++++++++
 start.c | 12 +++++++++++-
 2 files changed, 19 insertions(+), 1 deletion(-)
 create mode 100644 riscv.h

diff --git a/riscv.h b/riscv.h
new file mode 100644
index 0000000..6bf3df9
--- /dev/null
+++ b/riscv.h
@@ -0,0 +1,8 @@
+#include <types.h>
+
+/** Returns the current hart id */
+static inline u64 r_mhartid() {
+    u64 x;
+    asm volatile("csrr %0, mhartid" : "=r"(x));
+    return x;
+}
diff --git a/start.c b/start.c
index 3b923f8..e07633f 100644
--- a/start.c
+++ b/start.c
@@ -1,3 +1,6 @@
+#include <riscv.h>
+#include <types.h>
+
 /*
  * Number of CPU's For now, this is hard-coded here. It will likely be in a
  * header, or dynamically discovered in the future
@@ -25,7 +28,14 @@ char stack0[4096 * NCPU] __attribute__((aligned(16)));
 
 /* This is where entry.S drops us of. All cores land here */
 void start() {
-    uart_puts("Hello Neptune!\n");
+
+    u64 a = r_mhartid();
+    if(a == 0) {
+        uart_puts("Hello Neptune!\n");
+        uart_puts("Core number: ");
+        uart_putc(a + '0');
+        uart_putc('\n');
+    }
 
     /* Here we will do a bunch of initialization steps */