From 58bface3c9c5d27f0db1f087f0d8320396f29f4b Mon Sep 17 00:00:00 2001
From: Imbus <>
Date: Thu, 26 Jun 2025 06:24:01 +0200
Subject: [PATCH] Fix nasty bug related to spinlock panic when lock is already
 held, because the tread pointer was never set on a per-hart basis.

---
 riscv.h |  3 +++
 start.c | 11 +++++++++--
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/riscv.h b/riscv.h
index b614112..91b17b0 100644
--- a/riscv.h
+++ b/riscv.h
@@ -40,6 +40,9 @@ static inline u64 r_tp() {
     return x;
 }
 
+/** Write thread pointer */
+static inline void w_tp(u64 x) { asm volatile("mv tp, %0" : : "r"(x)); }
+
 /**
  * Read the value of the sstatus register.
  * (Supervisor Status Register)
diff --git a/start.c b/start.c
index 425059a..656ac65 100644
--- a/start.c
+++ b/start.c
@@ -1,6 +1,8 @@
 #include <config.h>
+#include <proc.h>
 #include <riscv.h>
 #include <spinlock.h>
+#include <string.h>
 #include <types.h>
 #include <uart.h>
 
@@ -18,8 +20,13 @@ volatile int    greeted = 0;
 
 /* This is where entry.S drops us of. All cores land here */
 void start() {
+    u64 id = r_mhartid();
 
-    u64 a = r_mhartid();
+    // Keep each CPU's hartid in its tp (thread pointer) register, for cpuid().
+    // This can then be retrieved with r_wp or cpuid(). It is used to index the
+    // cpus[] array in mycpu(), which in turn holds state for each individual
+    // cpu (struct Cpu).
+    w_tp(id);
 
     acquire(&sl);
 
@@ -29,7 +36,7 @@ void start() {
     }
 
     uart_puts("Hart number: ");
-    uart_putc(a + '0');
+    uart_putc(id + '0');
     uart_putc('\n');
 
     release(&sl);