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Some vocabulary in readme

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README.md
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@ -6,3 +6,23 @@ For a quick reference on RISC-V assembly:
Toolchains:
- https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack
- https://github.com/xpack-dev-tools/qemu-riscv-xpack/
---
| Register | Name | Privilege Level | Description |
|-------------|----------------------------|------------------|-----------------------------------------------------------------------------|
| `mstatus` | Machine Status Register | Machine | Holds global interrupt enable, previous privilege mode, etc. |
| `mtvec` | Machine Trap-Vector Base | Machine | Holds the base address of the trap handler (exception/interrupt entry). |
| `mepc` | Machine Exception PC | Machine | Stores the program counter at the time of the last trap. |
| `mcause` | Machine Cause Register | Machine | Indicates the cause of the last trap (interrupt or exception). |
| `satp` | Supervisor Address Translation and Protection | Supervisor | Controls page table base address and mode (e.g., Sv39, Sv48). |
| `sstatus` | Supervisor Status Register | Supervisor | Like `mstatus`, but accessible from supervisor mode. |
| `stvec` | Supervisor Trap-Vector Base| Supervisor | Like `mtvec`, but for supervisor mode traps. |
| `sepc` | Supervisor Exception PC | Supervisor | Like `mepc`, but for supervisor mode. |
| `scause` | Supervisor Cause Register | Supervisor | Like `mcause`, but for supervisor mode traps. |
| `sscratch` | Supervisor Scratch | Supervisor | Can be used to store temporary state across traps in supervisor mode. |
| `mscratch` | Machine Scratch | Machine | Like `sscratch`, but in machine mode. |
| `mcycle` | Machine Cycle Counter | Machine | Counts the number of cycles executed. |
| `mtime` | Machine Timer Register | Machine (via memory-mapped) | Used for timing and scheduling (not a CSR, but a memory-mapped register). |
| `mip` | Machine Interrupt Pending | Machine | Indicates pending interrupts. |
| `mie` | Machine Interrupt Enable | Machine | Controls which interrupts are enabled. |