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Purge fancy register macros, use inline assembly instead

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Imbus 2025-06-26 13:51:22 +02:00
parent d855404c01
commit d9896b4229
1 changed files with 5 additions and 43 deletions
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48
riscv.h
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@ -24,50 +24,12 @@ typedef u64 pte_t;
/** Page Table Type */ /** Page Table Type */
typedef u64 *pagetable_t; // 512 PTEs typedef u64 *pagetable_t; // 512 PTEs
// CSR numeric addresses
#define CSR_MSTATUS 0x300
#define CSR_MISA 0x301
#define CSR_MIE 0x304
#define CSR_MTVEC 0x305
#define CSR_MCOUNTEREN 0x306
#define CSR_MSCRATCH 0x340
#define CSR_MEPC 0x341
#define CSR_MCAUSE 0x342
#define CSR_MTVAL 0x343
#define CSR_MIP 0x344
#define CSR_MHARTID 0xF14
static inline u64 read_csr(u32 csr) {
u64 value;
asm volatile("csrr %0, %1" : "=r"(value) : "i"(csr));
return value;
}
static inline void write_csr(u32 csr, u64 value) {
asm volatile("csrw %0, %1" ::"i"(csr), "r"(value));
}
static inline u64 read_mstatus(void) { return read_csr(CSR_MSTATUS); }
static inline void write_mstatus(u64 val) { write_csr(CSR_MSTATUS, val); }
static inline u64 read_mcause(void) { return read_csr(CSR_MCAUSE); }
static inline u64 read_mtval(void) { return read_csr(CSR_MTVAL); }
static inline u64 read_mepc(void) { return read_csr(CSR_MEPC); }
static inline void write_mepc(u64 val) { write_csr(CSR_MEPC, val); }
static inline void write_mtvec(u64 val) { write_csr(CSR_MTVEC, val); }
static inline u64 read_mtvec(void) { return read_csr(CSR_MTVEC); }
/** Returns the current hart id */ /** Returns the current hart id */
static inline u64 read_mhartid(void) { return read_csr(CSR_MHARTID); } static inline u64 read_mhartid() {
u64 x;
// static inline u64 r_mhartid() { asm volatile("csrr %0, mhartid" : "=r"(x));
// u64 x; return x;
// asm volatile("csrr %0, mhartid" : "=r"(x)); }
// return x;
// }
/** Read thread pointer */ /** Read thread pointer */
static inline u64 read_tp() { static inline u64 read_tp() {