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No commits in common. "0562c2fe5a25f75d6243427b8eb3040475c7b631" and "ee2ddd7e8c2e385539092f51f5f45abf423d9f85" have entirely different histories.

4 changed files with 9 additions and 27 deletions

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@ -2,7 +2,7 @@
* Number of CPU's For now, this is hard-coded here. It will likely be
* dynamically discovered in the future.
*/
#define NCPU 4
#define NCPU 3
/* Maximum number of files open */
#define NOFILE 10

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@ -19,7 +19,7 @@ void spin_unlock(spinlock_t *l) {
// Optional: tiny pause/backoff (works even if Zihintpause isn't present).
// See: https://github.com/riscv/riscv-isa-manual/blob/main/src/zihintpause.adoc
static inline void cpu_relax(void) {
void cpu_relax(void) {
#if defined(__riscv_zihintpause)
__asm__ volatile("pause");
#else

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@ -8,4 +8,5 @@ typedef struct {
void spinlock_init(spinlock_t *l);
bool spin_trylock(spinlock_t *l);
void spin_unlock(spinlock_t *l);
void cpu_relax(void);
void spin_lock(spinlock_t *l);

27
start.c
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@ -18,14 +18,9 @@ char stack0[4096 * NCPU] __attribute__((aligned(16)));
/* Keep this here and sync on it until we have synchronized printf */
spinlock_t sl = {0};
volatile int hold = 1;
volatile int max_hart = 0;
/* This is where entry.S drops us of. All cores land here */
void start() {
// Do this first
__sync_fetch_and_add(&max_hart, 1);
__sync_synchronize();
u64 id = read_mhartid();
// Keep each CPU's hartid in its tp (thread pointer) register, for cpuid().
@ -40,29 +35,15 @@ void start() {
uart_puts("Hello Neptune!\n");
spinlock_init(&sl);
hold = 0;
} else {
}
while (hold);
}
// spin_lock(&sl);
//
// uart_puts("Hart number: ");
// uart_putc(id + '0');
// uart_putc('\n');
//
// spin_unlock(&sl);
if (id == 0) {
spin_lock(&sl);
uart_puts("Core count: ");
uart_putc(max_hart + '0');
uart_puts("Hart number: ");
uart_putc(id + '0');
uart_putc('\n');
if (max_hart == NCPU) {
uart_puts("All cores up!");
uart_putc('\n');
}
spin_unlock(&sl);
}
// We should not arrive here, but if we do, hang in a while on wfi.
while (1) __asm__ volatile("wfi"); // (Wait For Interrupt)