Nasty unfixed bug related to spinlock panics

lib/proc.c

@@ -2,7 +2,20 @@
 
 struct Cpu cpus[NCPU];
 
+/**
+ * Must be called with interrupts disabled, to prevent race with process being
+ * moved to a different CPU.
+ */
+int cpuid() {
+    int id = read_tp();
+    return id;
+}
+
 /**
  * Return this CPU's cpu struct. Interrupts must be disabled.
  */
-inline struct Cpu *mycpu(void) { return &cpus[read_tp()]; }
+struct Cpu *mycpu(void) {
+    int         id = cpuid();
+    struct Cpu *c = &cpus[id];
+    return c;
+}

lib/spinlock.c

@@ -4,10 +4,12 @@
  */
 
 // #include <lib/stdio.h>
+#include "string.h"
 #include <panic.h>
 #include <proc.h>
 #include <riscv.h>
 #include <spinlock.h>
+#include <uart.h>
 
 /**
  * The aquire() and release() functions control ownership of the lock.
@@ -99,6 +101,7 @@ void push_off(void) {
     intr_off();
     if (mycpu()->noff == 0)
         mycpu()->intena = old;
+
     mycpu()->noff += 1;
 }
 
@@ -106,8 +109,15 @@ void pop_off(void) {
     struct Cpu *c = mycpu();
     if (intr_get())
         panic("pop_off - interruptible");
-    if (c->noff < 1)
+    if (c->noff < 1) {
+        {
+            // TODO: Remove this block when fixed
+            char amt[100];
+            itoa(c->noff, amt, 10);
+            uart_puts(amt);
+        }
         panic("pop_off");
+    }
     c->noff -= 1;
     if (c->noff == 0 && c->intena)
         intr_on();

riscv.h

@@ -24,50 +24,12 @@ typedef u64 pte_t;
 /** Page Table Type */
 typedef u64 *pagetable_t; // 512 PTEs
 
-// CSR numeric addresses
-#define CSR_MSTATUS    0x300
-#define CSR_MISA       0x301
-#define CSR_MIE        0x304
-#define CSR_MTVEC      0x305
-#define CSR_MCOUNTEREN 0x306
-
-#define CSR_MSCRATCH 0x340
-#define CSR_MEPC     0x341
-#define CSR_MCAUSE   0x342
-#define CSR_MTVAL    0x343
-#define CSR_MIP      0x344
-
-#define CSR_MHARTID 0xF14
-
-static inline u64 read_csr(u32 csr) {
-    u64 value;
-    asm volatile("csrr %0, %1" : "=r"(value) : "i"(csr));
-    return value;
-}
-
-static inline void write_csr(u32 csr, u64 value) {
-    asm volatile("csrw %0, %1" ::"i"(csr), "r"(value));
-}
-
-static inline u64  read_mstatus(void) { return read_csr(CSR_MSTATUS); }
-static inline void write_mstatus(u64 val) { write_csr(CSR_MSTATUS, val); }
-
-static inline u64  read_mcause(void) { return read_csr(CSR_MCAUSE); }
-static inline u64  read_mtval(void) { return read_csr(CSR_MTVAL); }
-static inline u64  read_mepc(void) { return read_csr(CSR_MEPC); }
-static inline void write_mepc(u64 val) { write_csr(CSR_MEPC, val); }
-
-static inline void write_mtvec(u64 val) { write_csr(CSR_MTVEC, val); }
-static inline u64  read_mtvec(void) { return read_csr(CSR_MTVEC); }
-
 /** Returns the current hart id */
-static inline u64 read_mhartid(void) { return read_csr(CSR_MHARTID); }
-
-// static inline u64 r_mhartid() {
-//     u64 x;
-//     asm volatile("csrr %0, mhartid" : "=r"(x));
-//     return x;
-// }
+static inline u64 read_mhartid() {
+    u64 x;
+    asm volatile("csrr %0, mhartid" : "=r"(x));
+    return x;
+}
 
 /** Read thread pointer */
 static inline u64 read_tp() {