45 lines
1.3 KiB
C
45 lines
1.3 KiB
C
#include "ispinlock.h"
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void spinlock_init(spinlock_t *l) {
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l->v = 0;
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}
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__attribute__((warn_unused_result)) bool spin_trylock(spinlock_t *l) {
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uint32_t old;
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// old = xchg_acquire(&l->v, 1) using AMO
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__asm__ volatile("amoswap.w.aq %0, %2, (%1)\n" : "=&r"(old) : "r"(&l->v), "r"(1u) : "memory");
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return old == 0;
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}
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void spin_unlock(spinlock_t *l) {
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// Release: store 0 with .rl ordering.
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uint32_t dummy;
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__asm__ volatile("amoswap.w.rl %0, %2, (%1)\n" : "=&r"(dummy) : "r"(&l->v), "r"(0u) : "memory");
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}
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// Optional: tiny pause/backoff (works even if Zihintpause isn't present).
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// See: https://github.com/riscv/riscv-isa-manual/blob/main/src/zihintpause.adoc
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static inline void cpu_relax(void) {
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#if defined(__riscv_zihintpause)
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__asm__ volatile("pause");
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#else
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__asm__ volatile("nop");
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#endif
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}
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// Test-and-test-and-set acquire with polite spinning + exponential backoff.
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void spin_lock(spinlock_t *l) {
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unsigned backoff = 1;
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for (;;) {
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if (spin_trylock(l))
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return;
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// Contended: spin on plain loads (no AMO) until it looks free.
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while (__atomic_load_n(&l->v, __ATOMIC_RELAXED) != 0) {
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for (unsigned i = 0; i < backoff; ++i) cpu_relax();
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if (backoff < 1u << 12)
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backoff <<= 1;
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}
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// Try again; loop.
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}
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}
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