112 lines
3 KiB
C
112 lines
3 KiB
C
#ifndef RISCV_KERNEL_H
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#define RISCV_KERNEL_H
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#include <types.h>
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/** Page Size */
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#define PGSIZE 4096 // bytes per page
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// /** Page Shift, bits of offset within a page */
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#define PGSHIFT 12
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#define PGROUNDUP(sz) (((sz) + PGSIZE - 1) & ~(PGSIZE - 1))
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#define PGROUNDDOWN(a) (((a)) & ~(PGSIZE - 1))
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// Supervisor Status Register, sstatus
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#define SSTATUS_SPP (1L << 8) /** Supervisor Previous Privilege 1=S, 0=U */
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#define SSTATUS_SPIE (1L << 5) /** Supervisor Previous Interrupt Enable */
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#define SSTATUS_UPIE (1L << 4) /** User Previous Interrupt Enable */
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#define SSTATUS_SIE (1L << 1) /** Supervisor Interrupt Enable */
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#define SSTATUS_UIE (1L << 0) /** User Interrupt Enable */
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/** Page Table Entry Type */
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typedef u64 pte_t;
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/** Page Table Type */
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typedef u64 *pagetable_t; // 512 PTEs
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// CSR numeric addresses
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#define CSR_MSTATUS 0x300
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#define CSR_MISA 0x301
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#define CSR_MIE 0x304
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#define CSR_MTVEC 0x305
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#define CSR_MCOUNTEREN 0x306
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#define CSR_MSCRATCH 0x340
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#define CSR_MEPC 0x341
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#define CSR_MCAUSE 0x342
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#define CSR_MTVAL 0x343
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#define CSR_MIP 0x344
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#define CSR_MHARTID 0xF14
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static inline u64 read_csr(u32 csr) {
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u64 value;
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asm volatile("csrr %0, %1" : "=r"(value) : "i"(csr));
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return value;
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}
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static inline void write_csr(u32 csr, u64 value) {
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asm volatile("csrw %0, %1" ::"i"(csr), "r"(value));
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}
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static inline u64 read_mstatus(void) { return read_csr(CSR_MSTATUS); }
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static inline void write_mstatus(u64 val) { write_csr(CSR_MSTATUS, val); }
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static inline u64 read_mcause(void) { return read_csr(CSR_MCAUSE); }
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static inline u64 read_mtval(void) { return read_csr(CSR_MTVAL); }
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static inline u64 read_mepc(void) { return read_csr(CSR_MEPC); }
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static inline void write_mepc(u64 val) { write_csr(CSR_MEPC, val); }
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static inline void write_mtvec(u64 val) { write_csr(CSR_MTVEC, val); }
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static inline u64 read_mtvec(void) { return read_csr(CSR_MTVEC); }
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/** Returns the current hart id */
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static inline u64 read_mhartid(void) { return read_csr(CSR_MHARTID); }
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// static inline u64 r_mhartid() {
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// u64 x;
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// asm volatile("csrr %0, mhartid" : "=r"(x));
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// return x;
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// }
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/** Read thread pointer */
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static inline u64 read_tp() {
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u64 x;
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asm volatile("mv %0, tp" : "=r"(x));
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return x;
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}
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/** Write thread pointer */
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static inline void write_tp(u64 x) { asm volatile("mv tp, %0" : : "r"(x)); }
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/**
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* Read the value of the sstatus register.
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* (Supervisor Status Register)
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*/
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static inline u64 r_sstatus() {
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u64 x;
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asm volatile("csrr %0, sstatus" : "=r"(x));
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return x;
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}
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/**
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* Write a value to the sstatus register.
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* (Supervisor Status Register)
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*/
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static inline void w_sstatus(u64 x) {
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asm volatile("csrw sstatus, %0" : : "r"(x));
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}
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/** Enable device interrupts */
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static inline void intr_on() { w_sstatus(r_sstatus() | SSTATUS_SIE); }
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/** Disable device interrupts */
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static inline void intr_off() { w_sstatus(r_sstatus() & ~SSTATUS_SIE); }
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/** Are device interrupts enabled? */
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static inline int intr_get() {
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u64 x = r_sstatus();
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return (x & SSTATUS_SIE) != 0;
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}
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#endif
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