163 lines
4.1 KiB
C
163 lines
4.1 KiB
C
#ifndef RISCV_KERNEL_H
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#define RISCV_KERNEL_H
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#include <stdint.h>
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/** Page Size */
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#define PGSIZE 4096 // bytes per page
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// /** Page Shift, bits of offset within a page */
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#define PGSHIFT 12
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#define PGROUNDUP(sz) (((sz) + PGSIZE - 1) & ~(PGSIZE - 1))
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#define PGROUNDDOWN(a) (((a)) & ~(PGSIZE - 1))
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// Supervisor Status Register, sstatus
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#define SSTATUS_SPP (1L << 8) /** Supervisor Previous Privilege 1=S, 0=U */
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#define SSTATUS_SPIE (1L << 5) /** Supervisor Previous Interrupt Enable */
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#define SSTATUS_UPIE (1L << 4) /** User Previous Interrupt Enable */
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#define SSTATUS_SIE (1L << 1) /** Supervisor Interrupt Enable */
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#define SSTATUS_UIE (1L << 0) /** User Interrupt Enable */
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// Machine Status Register, mstatus
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#define MSTATUS_MPP_MASK (3L << 11) /** M-mode Previous Privilege */
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#define MSTATUS_MPP_M (3L << 11) /** M-mode Previous Privilege Machine-mode */
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#define MSTATUS_MPP_S (1L << 11) /** M-mode Previous Privilege Supervisor-mode */
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#define MSTATUS_MPP_U (0L << 11) /** M-mode Previous Privilege User-mode */
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#define MSTATUS_MIE (1L << 3) /** M-mode Interrupt Enable */
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/** Page Table Entry Type */
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typedef u64 pte_t;
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/** Page Table Type */
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typedef u64 *pagetable_t; // 512 PTEs
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/** Returns the current hart id */
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static inline u64 read_mhartid() {
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u64 x;
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asm volatile("csrr %0, mhartid" : "=r"(x));
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return x;
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}
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/** Read thread pointer */
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static inline u64 read_tp() {
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u64 x;
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asm volatile("mv %0, tp" : "=r"(x));
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return x;
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}
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/** Write thread pointer */
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static inline void write_tp(u64 x) {
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asm volatile("mv tp, %0" : : "r"(x));
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}
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/**
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* Read the value of the sstatus register.
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* (Supervisor Status Register)
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*/
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static inline u64 r_sstatus() {
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u64 x;
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asm volatile("csrr %0, sstatus" : "=r"(x));
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return x;
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}
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/**
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* Write a value to the sstatus register.
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* (Supervisor Status Register)
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*/
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static inline void w_sstatus(u64 x) {
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asm volatile("csrw sstatus, %0" : : "r"(x));
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}
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/** Enable device interrupts */
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static inline void intr_on() {
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w_sstatus(r_sstatus() | SSTATUS_SIE);
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}
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/** Disable device interrupts */
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static inline void intr_off() {
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w_sstatus(r_sstatus() & ~SSTATUS_SIE);
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}
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/** Are device interrupts enabled? */
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static inline int intr_get() {
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u64 x = r_sstatus();
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return (x & SSTATUS_SIE) != 0;
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}
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/** Read Machine Exception Delegation */
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static inline u64 r_medeleg() {
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u64 x;
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asm volatile("csrr %0, medeleg" : "=r"(x));
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return x;
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}
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/** Write Machine Exception Delegation */
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static inline void w_medeleg(u64 x) {
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asm volatile("csrw medeleg, %0" : : "r"(x));
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}
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/** Read Machine Interrupt Delegation */
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static inline u64 r_mideleg() {
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u64 x;
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asm volatile("csrr %0, mideleg" : "=r"(x));
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return x;
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}
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/** Write Machine Interrupt Delegation */
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static inline void w_mideleg(u64 x) {
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asm volatile("csrw mideleg, %0" : : "r"(x));
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}
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static inline u64 r_mstatus() {
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u64 x;
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asm volatile("csrr %0, mstatus" : "=r"(x));
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return x;
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}
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static inline void w_mstatus(u64 x) {
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asm volatile("csrw mstatus, %0" : : "r"(x));
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}
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/** Supervisor External Interrup Enable */
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#define SIE_SEIE (1L << 9)
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/** Supervisor Timer Interrupt Enable */
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#define SIE_STIE (1L << 5)
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/** Supervisor Software Interrupt Enable */
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#define SIE_SSIE (1L << 1)
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/** Read the value of the sie register. (Supervisor Interrupt Enable) */
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static inline u64 r_sie() {
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u64 x;
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asm volatile("csrr %0, sie" : "=r"(x));
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return x;
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}
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/** Write the valie to the sie rgister. (Supervisor Interrupt Enable) */
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static inline void w_sie(u64 x) {
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asm volatile("csrw sie, %0" : : "r"(x));
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}
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/** Machine External Interrupt Enable */
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#define MIE_MEIE (1L << 11)
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/** Machine Timer Interrupt Enable */
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#define MIE_MTIE (1L << 7)
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/** Machine Software Interrupt Enable */
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#define MIE_MSIE (1L << 3)
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/** Read the value of the mie register. (Machine Interrupt Enable) */
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static inline u64 r_mie() {
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u64 x;
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asm volatile("csrr %0, mie" : "=r"(x));
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return x;
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}
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/** Write the value to the mie register. (Machine Interrupt Enable) */
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static inline void w_mie(u64 x) {
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asm volatile("csrw mie, %0" : : "r"(x));
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}
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#endif // RISCV_KERNEL_H
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