34 lines
1.1 KiB
C
34 lines
1.1 KiB
C
/*
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* Number of CPU's For now, this is hard-coded here. It will likely be in a
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* header, or dynamically discovered in the future
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*/
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#define NCPU 3
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/* QEMU memory maps a UART device here. */
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#define UART_BASE ((char *)0x10000000)
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/** Send a single character to the UART device */
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void uart_putc(char c) { *UART_BASE = c; }
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/** Send a **NULL TERMINATED** string to the UART device */
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void uart_puts(const char *s) {
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while (*s) uart_putc(*s++);
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}
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/**
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* Allocate one stack per CPU (hart).
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* Each stack is 4096 bytes, aligned to 16 bytes for safety and performance.
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* The entry assembly code will calculate the proper stack address for the
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* current hart. For more info, read up on stack pointers and see: entry.S
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*/
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char stack0[4096 * NCPU] __attribute__((aligned(16)));
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/* This is where entry.S drops us of. All cores land here */
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void start() {
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uart_puts("Hello Neptune!\n");
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/* Here we will do a bunch of initialization steps */
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// We should not arrive here, but if we do, hang in a while on wfi.
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while (1) __asm__ volatile("wfi"); // (Wait For Interrupt)
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}
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