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Updating to zig master

Browse source 
Added cpu model


Moved logging to defer done log

Moved mem.init to bottom

Updated again to new zig master
This commit is contained in:
DrDeano 2020-04-12 22:26:34 +01:00
parent d17381c267
commit 1f97a5c6c8
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GPG key ID: 96188600582B9ED7
21 changed files with 157 additions and 135 deletions
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7
src/kernel/arch/x86/rtc.zig
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@ -252,6 +252,7 @@ fn enableInterrupts() void {
///
pub fn init() void {
log.logInfo("Init rtc\n", .{});
defer log.logInfo("Done rtc\n", .{});
// Register the interrupt handler
irq.registerIrq(pic.IRQ_REAL_TIME_CLOCK, rtcHandler) catch |err| switch (err) {
@ -276,16 +277,12 @@ pub fn init() void {
// Enable RTC interrupts
enableInterrupts();
// Read status register C to clear any interrupts that may have happened during set up
//const reg_c = cmos.readStatusRegister(cmos.StatusRegister.C, false);
// Can now enable interrupts
arch.enableInterrupts();
// Read status register C to clear any interrupts that may have happened during set up
const reg_c = cmos.readStatusRegister(cmos.StatusRegister.C, false);
log.logInfo("Done\n", .{});
if (build_options.rt_test) runtimeTests();
}