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Added RTC

Browse source 
Added I/O waits to PIC remapping

Added fmt step to build 

When building will format all the code to the standard

Fixed cascading interrupts

Re-named to selectAnd*Register. Moved switching on registers into emun


Removed build fmt step
This commit is contained in:
DrDeano 2020-01-15 19:50:41 +00:00
parent 96da426a3a
commit 7ab180f622
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GPG key ID: 96188600582B9ED7
8 changed files with 1336 additions and 14 deletions
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6
test/kernel/arch/x86/rt-test.py
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@ -10,12 +10,14 @@ def get_test_cases(TestCase):
TestCase("ISR tests", [r"ISR: Tested registered handlers", r"ISR: Tested opened IDT entries"]),
TestCase("IRQ init", [r"Init irq", r"Done"]),
TestCase("IRQ tests", [r"IRQ: Tested registered handlers", r"IRQ: Tested opened IDT entries"]),
TestCase("Paging init", [r"Init paging", r"Done"]),
TestCase("Paging tests", [r"Paging: Tested accessing unmapped memory", r"Paging: Tested accessing mapped memory"]),
TestCase("PIT init", [r"Init pit"]),
TestCase("PIT init", [r".+"], r"\[DEBUG\] "),
TestCase("PIT init", [r"Done"]),
TestCase("PIT tests", [r"PIT: Tested init", r"PIT: Tested wait ticks", r"PIT: Tested wait ticks 2"]),
TestCase("Paging init", [r"Init paging", r"Done"]),
TestCase("Paging tests", [r"Paging: Tested accessing unmapped memory", r"Paging: Tested accessing mapped memory"]),
TestCase("RTC init", [r"Init rtc", r"Done"]),
TestCase("RTC tests", [r"RTC: Tested init", r"RTC: Tested interrupts"]),
TestCase("Syscalls init", [r"Init syscalls", r"Done"]),
TestCase("Syscall tests", [r"Syscalls: Tested no args", r"Syscalls: Tested 1 arg", r"Syscalls: Tested 2 args", r"Syscalls: Tested 3 args", r"Syscalls: Tested 4 args", r"Syscalls: Tested 5 args"])
]