Fix T() style casts
This commit is contained in:
Sam Tebbs
parent
2587b9f16c
commit
7b2d4c1190
13 changed files with 287 additions and 287 deletions
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@ -410,7 +410,7 @@ pub fn spuriousIrq(irq_num: u8) bool {
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pub fn setMask(irq_num: u8) void {
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const port: u16 = if (irq_num < 8) MASTER_DATA_REG else SLAVE_DATA_REG;
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const shift = @intCast(u3, irq_num % 8);
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const value: u8 = arch.inb(port) | (u8(1) << shift);
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const value: u8 = arch.inb(port) | (@as(u8, 1) << shift);
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arch.outb(port, value);
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}
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@ -423,7 +423,7 @@ pub fn setMask(irq_num: u8) void {
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pub fn clearMask(irq_num: u8) void {
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const port: u16 = if (irq_num < 8) MASTER_DATA_REG else SLAVE_DATA_REG;
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const shift = @intCast(u3, irq_num % 8);
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const value: u8 = arch.inb(port) & ~(u8(1) << shift);
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const value: u8 = arch.inb(port) & ~(@as(u8, 1) << shift);
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arch.outb(port, value);
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}
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@ -451,8 +451,8 @@ pub fn init() void {
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sendDataSlave(ICW4_80x86_MODE);
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// Mask all interrupts
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sendDataMaster(u8(0xFF));
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sendDataSlave(u8(0xFF));
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sendDataMaster(0xFF);
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sendDataSlave(0xFF);
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log.logInfo("Done\n");
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@ -464,7 +464,7 @@ test "sendCommandMaster" {
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arch.initTest();
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defer arch.freeTest();
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const cmd = u8(10);
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const cmd: u8 = 10;
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arch.addTestParams("outb", MASTER_COMMAND_REG, cmd);
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@ -476,7 +476,7 @@ test "sendCommandSlave" {
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arch.initTest();
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defer arch.freeTest();
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const cmd = u8(10);
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const cmd: u8 = 10;
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arch.addTestParams("outb", SLAVE_COMMAND_REG, cmd);
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@ -488,7 +488,7 @@ test "sendDataMaster" {
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arch.initTest();
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defer arch.freeTest();
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const data = u8(10);
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const data: u8 = 10;
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arch.addTestParams("outb", MASTER_DATA_REG, data);
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@ -500,7 +500,7 @@ test "sendDataSlave" {
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arch.initTest();
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defer arch.freeTest();
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const data = u8(10);
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const data: u8 = 10;
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arch.addTestParams("outb", SLAVE_DATA_REG, data);
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@ -512,9 +512,9 @@ test "readDataMaster" {
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arch.initTest();
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defer arch.freeTest();
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arch.addTestParams("inb", MASTER_DATA_REG, u8(10));
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arch.addTestParams("inb", MASTER_DATA_REG, @as(u8, 10));
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expectEqual(u8(10), readDataMaster());
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expectEqual(@as(u8, 10), readDataMaster());
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}
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test "readDataSlave" {
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@ -522,9 +522,9 @@ test "readDataSlave" {
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arch.initTest();
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defer arch.freeTest();
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arch.addTestParams("inb", SLAVE_DATA_REG, u8(10));
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arch.addTestParams("inb", SLAVE_DATA_REG, @as(u8, 10));
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expectEqual(u8(10), readDataSlave());
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expectEqual(@as(u8, 10), readDataSlave());
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}
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test "readMasterIrr" {
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@ -532,10 +532,10 @@ test "readMasterIrr" {
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arch.initTest();
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defer arch.freeTest();
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arch.addTestParams("outb", MASTER_COMMAND_REG, u8(0x0A));
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arch.addTestParams("inb", MASTER_STATUS_REG, u8(10));
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arch.addTestParams("outb", MASTER_COMMAND_REG, @as(u8, 0x0A));
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arch.addTestParams("inb", MASTER_STATUS_REG, @as(u8, 10));
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expectEqual(u8(10), readMasterIrr());
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expectEqual(@as(u8, 10), readMasterIrr());
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}
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test "readSlaveIrr" {
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@ -543,10 +543,10 @@ test "readSlaveIrr" {
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arch.initTest();
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defer arch.freeTest();
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arch.addTestParams("outb", SLAVE_COMMAND_REG, u8(0x0A));
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arch.addTestParams("inb", SLAVE_STATUS_REG, u8(10));
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arch.addTestParams("outb", SLAVE_COMMAND_REG, @as(u8, 0x0A));
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arch.addTestParams("inb", SLAVE_STATUS_REG, @as(u8, 10));
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expectEqual(u8(10), readSlaveIrr());
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expectEqual(@as(u8, 10), readSlaveIrr());
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}
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test "readMasterIsr" {
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@ -554,10 +554,10 @@ test "readMasterIsr" {
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arch.initTest();
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defer arch.freeTest();
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arch.addTestParams("outb", MASTER_COMMAND_REG, u8(0x0B));
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arch.addTestParams("inb", MASTER_STATUS_REG, u8(10));
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arch.addTestParams("outb", MASTER_COMMAND_REG, @as(u8, 0x0B));
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arch.addTestParams("inb", MASTER_STATUS_REG, @as(u8, 10));
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expectEqual(u8(10), readMasterIsr());
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expectEqual(@as(u8, 10), readMasterIsr());
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}
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test "readSlaveIsr" {
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@ -565,10 +565,10 @@ test "readSlaveIsr" {
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arch.initTest();
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defer arch.freeTest();
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arch.addTestParams("outb", SLAVE_COMMAND_REG, u8(0x0B));
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arch.addTestParams("inb", SLAVE_STATUS_REG, u8(10));
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arch.addTestParams("outb", SLAVE_COMMAND_REG, @as(u8, 0x0B));
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arch.addTestParams("inb", SLAVE_STATUS_REG, @as(u8, 10));
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expectEqual(u8(10), readSlaveIsr());
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expectEqual(@as(u8, 10), readSlaveIsr());
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}
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test "sendEndOfInterrupt master only" {
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@ -576,7 +576,7 @@ test "sendEndOfInterrupt master only" {
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arch.initTest();
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defer arch.freeTest();
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var i = u8(0);
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var i: u8 = 0;
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while (i < 8) : (i += 1) {
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arch.addTestParams("outb", MASTER_COMMAND_REG, OCW2_END_OF_INTERRUPT);
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@ -589,7 +589,7 @@ test "sendEndOfInterrupt master and slave" {
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arch.initTest();
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defer arch.freeTest();
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var i = u8(8);
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var i: u8 = 8;
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while (i < 16) : (i += 1) {
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arch.addTestParams("outb", SLAVE_COMMAND_REG, OCW2_END_OF_INTERRUPT);
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arch.addTestParams("outb", MASTER_COMMAND_REG, OCW2_END_OF_INTERRUPT);
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@ -600,9 +600,9 @@ test "sendEndOfInterrupt master and slave" {
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test "spuriousIrq not spurious IRQ number" {
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// Pre testing
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expectEqual(u32(0), spurious_irq_counter);
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expectEqual(@as(u32, 0), spurious_irq_counter);
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var i = u8(0);
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var i: u8 = 0;
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while (i < 16) : (i += 1) {
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if (i != 7 and i != 15) {
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expectEqual(false, spuriousIrq(i));
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@ -610,7 +610,7 @@ test "spuriousIrq not spurious IRQ number" {
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}
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// Post testing
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expectEqual(u32(0), spurious_irq_counter);
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expectEqual(@as(u32, 0), spurious_irq_counter);
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// Clean up
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spurious_irq_counter = 0;
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@ -621,18 +621,18 @@ test "spuriousIrq spurious master IRQ number not spurious" {
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arch.initTest();
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defer arch.freeTest();
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arch.addTestParams("outb", MASTER_COMMAND_REG, u8(0x0B));
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arch.addTestParams("outb", MASTER_COMMAND_REG, @as(u8, 0x0B));
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// Return 0x80 from readMasterIsr() which will mean this was a real IRQ
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arch.addTestParams("inb", MASTER_STATUS_REG, u8(0x80));
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arch.addTestParams("inb", MASTER_STATUS_REG, @as(u8, 0x80));
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// Pre testing
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expectEqual(u32(0), spurious_irq_counter);
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expectEqual(@as(u32, 0), spurious_irq_counter);
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// Call function
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expectEqual(false, spuriousIrq(u8(7)));
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expectEqual(false, spuriousIrq(7));
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// Post testing
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expectEqual(u32(0), spurious_irq_counter);
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expectEqual(@as(u32, 0), spurious_irq_counter);
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// Clean up
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spurious_irq_counter = 0;
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@ -643,18 +643,18 @@ test "spuriousIrq spurious master IRQ number spurious" {
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arch.initTest();
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defer arch.freeTest();
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arch.addTestParams("outb", MASTER_COMMAND_REG, u8(0x0B));
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arch.addTestParams("outb", MASTER_COMMAND_REG, @as(u8, 0x0B));
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// Return 0x0 from readMasterIsr() which will mean this was a spurious IRQ
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arch.addTestParams("inb", MASTER_STATUS_REG, u8(0x0));
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arch.addTestParams("inb", MASTER_STATUS_REG, @as(u8, 0x0));
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// Pre testing
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expectEqual(u32(0), spurious_irq_counter);
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expectEqual(@as(u32, 0), spurious_irq_counter);
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// Call function
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expectEqual(true, spuriousIrq(u8(7)));
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expectEqual(true, spuriousIrq(7));
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// Post testing
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expectEqual(u32(1), spurious_irq_counter);
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expectEqual(@as(u32, 1), spurious_irq_counter);
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// Clean up
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spurious_irq_counter = 0;
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@ -665,18 +665,18 @@ test "spuriousIrq spurious slave IRQ number not spurious" {
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arch.initTest();
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defer arch.freeTest();
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arch.addTestParams("outb", SLAVE_COMMAND_REG, u8(0x0B));
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arch.addTestParams("outb", SLAVE_COMMAND_REG, @as(u8, 0x0B));
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// Return 0x80 from readSlaveIsr() which will mean this was a real IRQ
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arch.addTestParams("inb", SLAVE_STATUS_REG, u8(0x80));
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arch.addTestParams("inb", SLAVE_STATUS_REG, @as(u8, 0x80));
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// Pre testing
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expectEqual(u32(0), spurious_irq_counter);
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expectEqual(@as(u32, 0), spurious_irq_counter);
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// Call function
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expectEqual(false, spuriousIrq(u8(15)));
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expectEqual(false, spuriousIrq(15));
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// Post testing
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expectEqual(u32(0), spurious_irq_counter);
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expectEqual(@as(u32, 0), spurious_irq_counter);
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// Clean up
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spurious_irq_counter = 0;
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@ -687,20 +687,20 @@ test "spuriousIrq spurious slave IRQ number spurious" {
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arch.initTest();
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defer arch.freeTest();
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arch.addTestParams("outb", SLAVE_COMMAND_REG, u8(0x0B));
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arch.addTestParams("outb", SLAVE_COMMAND_REG, @as(u8, 0x0B));
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// Return 0x0 from readSlaveIsr() which will mean this was a spurious IRQ
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arch.addTestParams("inb", SLAVE_STATUS_REG, u8(0x0));
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arch.addTestParams("inb", SLAVE_STATUS_REG, @as(u8, 0x0));
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// A EOI will be sent for a spurious IRQ 15
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arch.addTestParams("outb", MASTER_COMMAND_REG, OCW2_END_OF_INTERRUPT);
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// Pre testing
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expectEqual(u32(0), spurious_irq_counter);
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expectEqual(@as(u32, 0), spurious_irq_counter);
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// Call function
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expectEqual(true, spuriousIrq(u8(15)));
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expectEqual(true, spuriousIrq(15));
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// Post testing
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expectEqual(u32(1), spurious_irq_counter);
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expectEqual(@as(u32, 1), spurious_irq_counter);
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// Clean up
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spurious_irq_counter = 0;
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@ -712,11 +712,11 @@ test "setMask master IRQ masked" {
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defer arch.freeTest();
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// Going to assume all bits are masked out
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arch.addTestParams("inb", MASTER_DATA_REG, u8(0xFF));
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arch.addTestParams("inb", MASTER_DATA_REG, @as(u8, 0xFF));
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// Expect the 2nd bit to be set
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arch.addTestParams("outb", MASTER_DATA_REG, u8(0xFF));
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arch.addTestParams("outb", MASTER_DATA_REG, @as(u8, 0xFF));
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setMask(u8(1));
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setMask(1);
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}
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test "setMask master IRQ unmasked" {
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@ -725,11 +725,11 @@ test "setMask master IRQ unmasked" {
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defer arch.freeTest();
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// IRQ already unmasked
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arch.addTestParams("inb", MASTER_DATA_REG, u8(0xFD));
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arch.addTestParams("inb", MASTER_DATA_REG, @as(u8, 0xFD));
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// Expect the 2nd bit to be set
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arch.addTestParams("outb", MASTER_DATA_REG, u8(0xFF));
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arch.addTestParams("outb", MASTER_DATA_REG, @as(u8, 0xFF));
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setMask(u8(1));
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setMask(1);
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}
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test "clearMask master IRQ masked" {
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@ -738,11 +738,11 @@ test "clearMask master IRQ masked" {
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defer arch.freeTest();
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// Going to assume all bits are masked out
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arch.addTestParams("inb", MASTER_DATA_REG, u8(0xFF));
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arch.addTestParams("inb", MASTER_DATA_REG, @as(u8, 0xFF));
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// Expect the 2nd bit to be clear
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arch.addTestParams("outb", MASTER_DATA_REG, u8(0xFD));
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arch.addTestParams("outb", MASTER_DATA_REG, @as(u8, 0xFD));
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clearMask(u8(1));
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clearMask(1);
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}
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test "clearMask master IRQ unmasked" {
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@ -751,11 +751,11 @@ test "clearMask master IRQ unmasked" {
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defer arch.freeTest();
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// IRQ already unmasked
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arch.addTestParams("inb", MASTER_DATA_REG, u8(0xFD));
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arch.addTestParams("inb", MASTER_DATA_REG, @as(u8, 0xFD));
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// Expect the 2nd bit to still be clear
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arch.addTestParams("outb", MASTER_DATA_REG, u8(0xFD));
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arch.addTestParams("outb", MASTER_DATA_REG, @as(u8, 0xFD));
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clearMask(u8(1));
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clearMask(1);
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}
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test "init" {
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@ -783,9 +783,9 @@ test "init" {
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SLAVE_DATA_REG,
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ICW4_80x86_MODE,
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MASTER_DATA_REG,
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u8(0xFF),
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@as(u8, 0xFF),
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SLAVE_DATA_REG,
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u8(0xFF),
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@as(u8, 0xFF),
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);
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init();
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