Update code to work with zig master
This commit is contained in:
Sam Tebbs
parent
4b870d3a65
commit
91b2a61acf
26 changed files with 476 additions and 438 deletions
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@ -424,7 +424,7 @@ pub fn setTssStack(esp0: u32) void {
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/// Initialise the Global Descriptor table.
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///
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pub fn init() void {
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log.logInfo("Init gdt\n");
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log.logInfo("Init gdt\n", .{});
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// Initiate TSS
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gdt_entries[TSS_INDEX] = makeEntry(@intCast(u32, @ptrToInt(&tss)), @sizeOf(TtsEntry) - 1, TSS_SEGMENT, NULL_FLAGS);
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@ -437,7 +437,7 @@ pub fn init() void {
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// Load the TSS
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arch.ltr(TSS_OFFSET);
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log.logInfo("Done\n");
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log.logInfo("Done\n", .{});
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if (build_options.rt_test) runtimeTests();
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}
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@ -639,7 +639,7 @@ test "init" {
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arch.initTest();
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defer arch.freeTest();
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arch.addTestParams("ltr", TSS_OFFSET);
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arch.addTestParams("ltr", .{TSS_OFFSET});
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arch.addConsumeFunction("lgdt", mock_lgdt);
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@ -681,5 +681,5 @@ fn rt_loadedGDTSuccess() void {
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///
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fn runtimeTests() void {
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rt_loadedGDTSuccess();
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log.logInfo("GDT: Tested loading GDT\n");
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log.logInfo("GDT: Tested loading GDT\n", .{});
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}
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@ -179,12 +179,12 @@ pub fn openInterruptGate(index: u8, handler: InterruptHandler) IdtError!void {
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/// Initialise the Interrupt descriptor table
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///
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pub fn init() void {
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log.logInfo("Init idt\n");
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log.logInfo("Init idt\n", .{});
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idt_ptr.base = @intCast(u32, @ptrToInt(&idt_entries));
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arch.lidt(&idt_ptr);
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log.logInfo("Done\n");
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log.logInfo("Done\n", .{});
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if (build_options.rt_test) runtimeTests();
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}
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@ -327,7 +327,7 @@ fn rt_loadedIDTSuccess() void {
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const loaded_idt = arch.sidt();
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expect(idt_ptr.limit == loaded_idt.limit);
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expect(idt_ptr.base == loaded_idt.base);
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log.logInfo("IDT: Tested loading IDT\n");
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log.logInfo("IDT: Tested loading IDT\n", .{});
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}
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///
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@ -44,7 +44,7 @@ var irq_handlers: [NUMBER_OF_ENTRIES]?IrqHandler = [_]?IrqHandler{null} ** NUMBE
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export fn irqHandler(ctx: *arch.InterruptContext) void {
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// Get the IRQ index, by getting the interrupt number and subtracting the offset.
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if (ctx.int_num < IRQ_OFFSET) {
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panic(@errorReturnTrace(), "Not an IRQ number: {}\n", ctx.int_num);
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panic(@errorReturnTrace(), "Not an IRQ number: {}\n", .{ctx.int_num});
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}
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const irq_offset = ctx.int_num - IRQ_OFFSET;
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@ -59,10 +59,10 @@ export fn irqHandler(ctx: *arch.InterruptContext) void {
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pic.sendEndOfInterrupt(irq_num);
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}
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} else {
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panic(@errorReturnTrace(), "IRQ not registered: {}", irq_num);
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panic(@errorReturnTrace(), "IRQ not registered: {}", .{irq_num});
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}
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} else {
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panic(@errorReturnTrace(), "Invalid IRQ index: {}", irq_offset);
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panic(@errorReturnTrace(), "Invalid IRQ index: {}", .{irq_offset});
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}
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}
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@ -76,7 +76,7 @@ export fn irqHandler(ctx: *arch.InterruptContext) void {
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fn openIrq(index: u8, handler: idt.InterruptHandler) void {
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idt.openInterruptGate(index, handler) catch |err| switch (err) {
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error.IdtEntryExists => {
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panic(@errorReturnTrace(), "Error opening IRQ number: {} exists", index);
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panic(@errorReturnTrace(), "Error opening IRQ number: {} exists", .{index});
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},
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};
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}
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@ -128,14 +128,14 @@ pub fn registerIrq(irq_num: u8, handler: IrqHandler) IrqError!void {
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/// the IDT interrupt gates for each IRQ.
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///
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pub fn init() void {
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log.logInfo("Init irq\n");
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log.logInfo("Init irq\n", .{});
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comptime var i = IRQ_OFFSET;
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inline while (i < IRQ_OFFSET + 16) : (i += 1) {
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openIrq(i, interrupts.getInterruptStub(i));
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}
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log.logInfo("Done\n");
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log.logInfo("Done\n", .{});
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if (build_options.rt_test) runtimeTests();
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}
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@ -152,7 +152,7 @@ test "openIrq" {
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const handler = testFunction0;
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const ret: idt.IdtError!void = {};
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idt.addTestParams("openInterruptGate", index, handler, ret);
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idt.addTestParams("openInterruptGate", .{ index, handler, ret });
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openIrq(index, handler);
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}
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@ -171,7 +171,7 @@ test "registerIrq re-register irq handler" {
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pic.initTest();
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defer pic.freeTest();
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pic.addTestParams("clearMask", @as(u16, 0));
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pic.addTestParams("clearMask", .{@as(u16, 0)});
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// Pre testing
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for (irq_handlers) |h| {
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@ -200,7 +200,7 @@ test "registerIrq register irq handler" {
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pic.initTest();
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defer pic.freeTest();
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pic.addTestParams("clearMask", @as(u16, 0));
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pic.addTestParams("clearMask", .{@as(u16, 0)});
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// Pre testing
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for (irq_handlers) |h| {
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@ -234,11 +234,11 @@ fn rt_unregisteredHandlers() void {
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// Ensure all ISR are not registered yet
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for (irq_handlers) |h, i| {
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if (h) |_| {
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panic(@errorReturnTrace(), "Handler found for IRQ: {}-{}\n", i, h);
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panic(@errorReturnTrace(), "Handler found for IRQ: {}-{}\n", .{ i, h });
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}
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}
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log.logInfo("IRQ: Tested registered handlers\n");
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log.logInfo("IRQ: Tested registered handlers\n", .{});
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}
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///
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@ -251,12 +251,12 @@ fn rt_openedIdtEntries() void {
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for (idt_entries) |entry, i| {
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if (i >= IRQ_OFFSET and isValidIrq(i - IRQ_OFFSET)) {
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if (!idt.isIdtOpen(entry)) {
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panic(@errorReturnTrace(), "IDT entry for {} is not open\n", i);
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panic(@errorReturnTrace(), "IDT entry for {} is not open\n", .{i});
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}
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}
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}
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log.logInfo("IRQ: Tested opened IDT entries\n");
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log.logInfo("IRQ: Tested opened IDT entries\n", .{});
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}
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///
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@ -150,18 +150,18 @@ export fn isrHandler(ctx: *arch.InterruptContext) void {
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if (syscall_handler) |handler| {
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handler(ctx);
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} else {
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panic(@errorReturnTrace(), "Syscall handler not registered\n");
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panic(@errorReturnTrace(), "Syscall handler not registered\n", .{});
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}
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} else {
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if (isr_handlers[isr_num]) |handler| {
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// Regular ISR exception, if there is one registered.
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handler(ctx);
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} else {
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panic(@errorReturnTrace(), "ISR not registered to: {}-{}\n", isr_num, exception_msg[isr_num]);
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panic(@errorReturnTrace(), "ISR not registered to: {}-{}\n", .{ isr_num, exception_msg[isr_num] });
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}
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}
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} else {
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panic(@errorReturnTrace(), "Invalid ISR index: {}\n", isr_num);
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panic(@errorReturnTrace(), "Invalid ISR index: {}\n", .{isr_num});
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}
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}
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@ -175,7 +175,7 @@ export fn isrHandler(ctx: *arch.InterruptContext) void {
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fn openIsr(index: u8, handler: idt.InterruptHandler) void {
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idt.openInterruptGate(index, handler) catch |err| switch (err) {
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error.IdtEntryExists => {
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panic(@errorReturnTrace(), "Error opening ISR number: {} exists\n", index);
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panic(@errorReturnTrace(), "Error opening ISR number: {} exists\n", .{index});
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},
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};
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}
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@ -234,7 +234,7 @@ pub fn registerIsr(isr_num: u16, handler: IsrHandler) IsrError!void {
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/// Initialise the exception and opening up all the IDT interrupt gates for each exception.
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///
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pub fn init() void {
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log.logInfo("Init isr\n");
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log.logInfo("Init isr\n", .{});
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comptime var i = 0;
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inline while (i < 32) : (i += 1) {
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@ -243,7 +243,7 @@ pub fn init() void {
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openIsr(syscalls.INTERRUPT, interrupts.getInterruptStub(syscalls.INTERRUPT));
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log.logInfo("Done\n");
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log.logInfo("Done\n", .{});
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if (build_options.rt_test) runtimeTests();
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}
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@ -262,7 +262,7 @@ test "openIsr" {
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const handler = testFunction0;
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const ret: idt.IdtError!void = {};
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idt.addTestParams("openInterruptGate", index, handler, ret);
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idt.addTestParams("openInterruptGate", .{ index, handler, ret });
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openIsr(index, handler);
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}
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@ -363,15 +363,15 @@ fn rt_unregisteredHandlers() void {
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// Ensure all ISR are not registered yet
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for (isr_handlers) |h, i| {
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if (h) |_| {
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panic(@errorReturnTrace(), "Handler found for ISR: {}-{}\n", i, h);
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panic(@errorReturnTrace(), "Handler found for ISR: {}-{}\n", .{ i, h });
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}
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}
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if (syscall_handler) |h| {
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panic(@errorReturnTrace(), "Pre-testing failed for syscall: {}\n", h);
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panic(@errorReturnTrace(), "Pre-testing failed for syscall: {}\n", .{h});
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}
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log.logInfo("ISR: Tested registered handlers\n");
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log.logInfo("ISR: Tested registered handlers\n", .{});
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}
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///
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@ -384,12 +384,12 @@ fn rt_openedIdtEntries() void {
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for (idt_entries) |entry, i| {
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if (isValidIsr(i)) {
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if (!idt.isIdtOpen(entry)) {
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panic(@errorReturnTrace(), "IDT entry for {} is not open\n", i);
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panic(@errorReturnTrace(), "IDT entry for {} is not open\n", .{i});
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}
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}
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}
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log.logInfo("ISR: Tested opened IDT entries\n");
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log.logInfo("ISR: Tested opened IDT entries\n", .{});
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}
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///
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@ -292,7 +292,7 @@ fn pageFault(state: *arch.InterruptContext) void {
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/// IN allocator: *std.mem.Allocator - The allocator to use
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///
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pub fn init(mb_info: *multiboot.multiboot_info_t, mem_profile: *const MemProfile, allocator: *std.mem.Allocator) void {
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log.logInfo("Init paging\n");
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log.logInfo("Init paging\n", .{});
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// Calculate start and end of mapping
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const v_start = std.mem.alignBackward(@ptrToInt(mem_profile.vaddr_start), PAGE_SIZE_4KB);
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const v_end = std.mem.alignForward(@ptrToInt(mem_profile.vaddr_end) + mem_profile.fixed_alloc_size, PAGE_SIZE_4KB);
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@ -300,14 +300,14 @@ pub fn init(mb_info: *multiboot.multiboot_info_t, mem_profile: *const MemProfile
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const p_end = std.mem.alignForward(@ptrToInt(mem_profile.physaddr_end) + mem_profile.fixed_alloc_size, PAGE_SIZE_4KB);
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var tmp = allocator.alignedAlloc(Directory, @truncate(u29, PAGE_SIZE_4KB), 1) catch |e| {
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panic(@errorReturnTrace(), "Failed to allocate page directory: {}\n", e);
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panic(@errorReturnTrace(), "Failed to allocate page directory: {}\n", .{e});
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};
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var kernel_directory = @ptrCast(*Directory, tmp.ptr);
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@memset(@ptrCast([*]u8, kernel_directory), 0, @sizeOf(Directory));
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// Map in kernel
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mapDir(kernel_directory, v_start, v_end, p_start, p_end, allocator) catch |e| {
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panic(@errorReturnTrace(), "Failed to map kernel directory: {}\n", e);
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panic(@errorReturnTrace(), "Failed to map kernel directory: {}\n", .{e});
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};
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const tty_addr = tty.getVideoBufferAddress();
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// If the previous mapping space didn't cover the tty buffer, do so now
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@ -315,7 +315,7 @@ pub fn init(mb_info: *multiboot.multiboot_info_t, mem_profile: *const MemProfile
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const tty_phys = mem.virtToPhys(tty_addr);
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const tty_buff_size = 32 * 1024;
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mapDir(kernel_directory, tty_addr, tty_addr + tty_buff_size, tty_phys, tty_phys + tty_buff_size, allocator) catch |e| {
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panic(@errorReturnTrace(), "Failed to map vga buffer in kernel directory: {}\n", e);
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panic(@errorReturnTrace(), "Failed to map vga buffer in kernel directory: {}\n", .{e});
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};
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}
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@ -325,7 +325,7 @@ pub fn init(mb_info: *multiboot.multiboot_info_t, mem_profile: *const MemProfile
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if (v_start > mb_info_addr) {
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const mb_info_end = mb_info_addr + PAGE_SIZE_4MB / 2;
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mapDir(kernel_directory, mb_info_addr, mb_info_end, mem.virtToPhys(mb_info_addr), mem.virtToPhys(mb_info_end), allocator) catch |e| {
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panic(@errorReturnTrace(), "Failed to map mb_info in kernel directory: {}\n", e);
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panic(@errorReturnTrace(), "Failed to map mb_info in kernel directory: {}\n", .{e});
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};
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}
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@ -334,12 +334,12 @@ pub fn init(mb_info: *multiboot.multiboot_info_t, mem_profile: *const MemProfile
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const mod_v_struct_start = std.mem.alignBackward(@ptrToInt(module), PAGE_SIZE_4KB);
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const mod_v_struct_end = std.mem.alignForward(mod_v_struct_start + @sizeOf(multiboot.multiboot_module_t), PAGE_SIZE_4KB);
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mapDir(kernel_directory, mod_v_struct_start, mod_v_struct_end, mem.virtToPhys(mod_v_struct_start), mem.virtToPhys(mod_v_struct_end), allocator) catch |e| {
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panic(@errorReturnTrace(), "Failed to map module struct: {}\n", e);
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panic(@errorReturnTrace(), "Failed to map module struct: {}\n", .{e});
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};
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const mod_p_start = std.mem.alignBackward(module.mod_start, PAGE_SIZE_4KB);
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const mod_p_end = std.mem.alignForward(module.mod_end, PAGE_SIZE_4KB);
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mapDir(kernel_directory, mem.physToVirt(mod_p_start), mem.physToVirt(mod_p_end), mod_p_start, mod_p_end, allocator) catch |e| {
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panic(@errorReturnTrace(), "Failed to map boot module in kernel directory: {}\n", e);
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panic(@errorReturnTrace(), "Failed to map boot module in kernel directory: {}\n", .{e});
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};
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}
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@ -349,9 +349,9 @@ pub fn init(mb_info: *multiboot.multiboot_info_t, mem_profile: *const MemProfile
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: [addr] "{eax}" (dir_physaddr)
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);
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isr.registerIsr(isr.PAGE_FAULT, if (options.rt_test) rt_pageFault else pageFault) catch |e| {
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panic(@errorReturnTrace(), "Failed to register page fault ISR: {}\n", e);
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panic(@errorReturnTrace(), "Failed to register page fault ISR: {}\n", .{e});
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};
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log.logInfo("Done\n");
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log.logInfo("Done\n", .{});
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if (options.rt_test) runtimeTests(v_end);
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}
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@ -482,7 +482,7 @@ fn rt_accessUnmappedMem(v_end: u32) void {
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\\rt_fault_callback:
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);
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testing.expect(faulted);
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log.logInfo("Paging: Tested accessing unmapped memory\n");
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log.logInfo("Paging: Tested accessing unmapped memory\n", .{});
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}
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fn rt_accessMappedMem(v_end: u32) void {
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@ -496,7 +496,7 @@ fn rt_accessMappedMem(v_end: u32) void {
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\\rt_fault_callback2:
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);
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testing.expect(!faulted);
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log.logInfo("Paging: Tested accessing mapped memory\n");
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log.logInfo("Paging: Tested accessing mapped memory\n", .{});
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}
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fn runtimeTests(v_end: u32) void {
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@ -432,7 +432,7 @@ pub fn clearMask(irq_num: u8) void {
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/// by Intel up to 0x1F. So this will move the IRQs from 0x00-0x0F to 0x20-0x2F.
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///
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pub fn init() void {
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log.logInfo("Init pic\n");
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log.logInfo("Init pic\n", .{});
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// Initiate
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sendCommandMaster(ICW1_INITIALISATION | ICW1_EXPECT_ICW4);
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@ -454,7 +454,7 @@ pub fn init() void {
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sendDataMaster(0xFF);
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sendDataSlave(0xFF);
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log.logInfo("Done\n");
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log.logInfo("Done\n", .{});
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if (build_options.rt_test) runtimeTests();
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}
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@ -466,7 +466,7 @@ test "sendCommandMaster" {
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const cmd: u8 = 10;
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arch.addTestParams("outb", MASTER_COMMAND_REG, cmd);
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arch.addTestParams("outb", .{ MASTER_COMMAND_REG, cmd });
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sendCommandMaster(cmd);
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}
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@ -478,7 +478,7 @@ test "sendCommandSlave" {
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const cmd: u8 = 10;
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arch.addTestParams("outb", SLAVE_COMMAND_REG, cmd);
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arch.addTestParams("outb", .{ SLAVE_COMMAND_REG, cmd });
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sendCommandSlave(cmd);
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}
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@ -490,7 +490,7 @@ test "sendDataMaster" {
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|||
|
||||
const data: u8 = 10;
|
||||
|
||||
arch.addTestParams("outb", MASTER_DATA_REG, data);
|
||||
arch.addTestParams("outb", .{ MASTER_DATA_REG, data });
|
||||
|
||||
sendDataMaster(data);
|
||||
}
|
||||
|
|
@ -502,7 +502,7 @@ test "sendDataSlave" {
|
|||
|
||||
const data: u8 = 10;
|
||||
|
||||
arch.addTestParams("outb", SLAVE_DATA_REG, data);
|
||||
arch.addTestParams("outb", .{ SLAVE_DATA_REG, data });
|
||||
|
||||
sendDataSlave(data);
|
||||
}
|
||||
|
|
@ -512,7 +512,7 @@ test "readDataMaster" {
|
|||
arch.initTest();
|
||||
defer arch.freeTest();
|
||||
|
||||
arch.addTestParams("inb", MASTER_DATA_REG, @as(u8, 10));
|
||||
arch.addTestParams("inb", .{ MASTER_DATA_REG, @as(u8, 10) });
|
||||
|
||||
expectEqual(@as(u8, 10), readDataMaster());
|
||||
}
|
||||
|
|
@ -522,7 +522,7 @@ test "readDataSlave" {
|
|||
arch.initTest();
|
||||
defer arch.freeTest();
|
||||
|
||||
arch.addTestParams("inb", SLAVE_DATA_REG, @as(u8, 10));
|
||||
arch.addTestParams("inb", .{ SLAVE_DATA_REG, @as(u8, 10) });
|
||||
|
||||
expectEqual(@as(u8, 10), readDataSlave());
|
||||
}
|
||||
|
|
@ -532,8 +532,8 @@ test "readMasterIrr" {
|
|||
arch.initTest();
|
||||
defer arch.freeTest();
|
||||
|
||||
arch.addTestParams("outb", MASTER_COMMAND_REG, @as(u8, 0x0A));
|
||||
arch.addTestParams("inb", MASTER_STATUS_REG, @as(u8, 10));
|
||||
arch.addTestParams("outb", .{ MASTER_COMMAND_REG, @as(u8, 0x0A) });
|
||||
arch.addTestParams("inb", .{ MASTER_STATUS_REG, @as(u8, 10) });
|
||||
|
||||
expectEqual(@as(u8, 10), readMasterIrr());
|
||||
}
|
||||
|
|
@ -543,8 +543,8 @@ test "readSlaveIrr" {
|
|||
arch.initTest();
|
||||
defer arch.freeTest();
|
||||
|
||||
arch.addTestParams("outb", SLAVE_COMMAND_REG, @as(u8, 0x0A));
|
||||
arch.addTestParams("inb", SLAVE_STATUS_REG, @as(u8, 10));
|
||||
arch.addTestParams("outb", .{ SLAVE_COMMAND_REG, @as(u8, 0x0A) });
|
||||
arch.addTestParams("inb", .{ SLAVE_STATUS_REG, @as(u8, 10) });
|
||||
|
||||
expectEqual(@as(u8, 10), readSlaveIrr());
|
||||
}
|
||||
|
|
@ -554,8 +554,8 @@ test "readMasterIsr" {
|
|||
arch.initTest();
|
||||
defer arch.freeTest();
|
||||
|
||||
arch.addTestParams("outb", MASTER_COMMAND_REG, @as(u8, 0x0B));
|
||||
arch.addTestParams("inb", MASTER_STATUS_REG, @as(u8, 10));
|
||||
arch.addTestParams("outb", .{ MASTER_COMMAND_REG, @as(u8, 0x0B) });
|
||||
arch.addTestParams("inb", .{ MASTER_STATUS_REG, @as(u8, 10) });
|
||||
|
||||
expectEqual(@as(u8, 10), readMasterIsr());
|
||||
}
|
||||
|
|
@ -565,8 +565,8 @@ test "readSlaveIsr" {
|
|||
arch.initTest();
|
||||
defer arch.freeTest();
|
||||
|
||||
arch.addTestParams("outb", SLAVE_COMMAND_REG, @as(u8, 0x0B));
|
||||
arch.addTestParams("inb", SLAVE_STATUS_REG, @as(u8, 10));
|
||||
arch.addTestParams("outb", .{ SLAVE_COMMAND_REG, @as(u8, 0x0B) });
|
||||
arch.addTestParams("inb", .{ SLAVE_STATUS_REG, @as(u8, 10) });
|
||||
|
||||
expectEqual(@as(u8, 10), readSlaveIsr());
|
||||
}
|
||||
|
|
@ -578,7 +578,7 @@ test "sendEndOfInterrupt master only" {
|
|||
|
||||
var i: u8 = 0;
|
||||
while (i < 8) : (i += 1) {
|
||||
arch.addTestParams("outb", MASTER_COMMAND_REG, OCW2_END_OF_INTERRUPT);
|
||||
arch.addTestParams("outb", .{ MASTER_COMMAND_REG, OCW2_END_OF_INTERRUPT });
|
||||
|
||||
sendEndOfInterrupt(i);
|
||||
}
|
||||
|
|
@ -591,8 +591,8 @@ test "sendEndOfInterrupt master and slave" {
|
|||
|
||||
var i: u8 = 8;
|
||||
while (i < 16) : (i += 1) {
|
||||
arch.addTestParams("outb", SLAVE_COMMAND_REG, OCW2_END_OF_INTERRUPT);
|
||||
arch.addTestParams("outb", MASTER_COMMAND_REG, OCW2_END_OF_INTERRUPT);
|
||||
arch.addTestParams("outb", .{ SLAVE_COMMAND_REG, OCW2_END_OF_INTERRUPT });
|
||||
arch.addTestParams("outb", .{ MASTER_COMMAND_REG, OCW2_END_OF_INTERRUPT });
|
||||
|
||||
sendEndOfInterrupt(i);
|
||||
}
|
||||
|
|
@ -621,9 +621,9 @@ test "spuriousIrq spurious master IRQ number not spurious" {
|
|||
arch.initTest();
|
||||
defer arch.freeTest();
|
||||
|
||||
arch.addTestParams("outb", MASTER_COMMAND_REG, @as(u8, 0x0B));
|
||||
arch.addTestParams("outb", .{ MASTER_COMMAND_REG, @as(u8, 0x0B) });
|
||||
// Return 0x80 from readMasterIsr() which will mean this was a real IRQ
|
||||
arch.addTestParams("inb", MASTER_STATUS_REG, @as(u8, 0x80));
|
||||
arch.addTestParams("inb", .{ MASTER_STATUS_REG, @as(u8, 0x80) });
|
||||
|
||||
// Pre testing
|
||||
expectEqual(@as(u32, 0), spurious_irq_counter);
|
||||
|
|
@ -643,9 +643,9 @@ test "spuriousIrq spurious master IRQ number spurious" {
|
|||
arch.initTest();
|
||||
defer arch.freeTest();
|
||||
|
||||
arch.addTestParams("outb", MASTER_COMMAND_REG, @as(u8, 0x0B));
|
||||
arch.addTestParams("outb", .{ MASTER_COMMAND_REG, @as(u8, 0x0B) });
|
||||
// Return 0x0 from readMasterIsr() which will mean this was a spurious IRQ
|
||||
arch.addTestParams("inb", MASTER_STATUS_REG, @as(u8, 0x0));
|
||||
arch.addTestParams("inb", .{ MASTER_STATUS_REG, @as(u8, 0x0) });
|
||||
|
||||
// Pre testing
|
||||
expectEqual(@as(u32, 0), spurious_irq_counter);
|
||||
|
|
@ -665,9 +665,9 @@ test "spuriousIrq spurious slave IRQ number not spurious" {
|
|||
arch.initTest();
|
||||
defer arch.freeTest();
|
||||
|
||||
arch.addTestParams("outb", SLAVE_COMMAND_REG, @as(u8, 0x0B));
|
||||
arch.addTestParams("outb", .{ SLAVE_COMMAND_REG, @as(u8, 0x0B) });
|
||||
// Return 0x80 from readSlaveIsr() which will mean this was a real IRQ
|
||||
arch.addTestParams("inb", SLAVE_STATUS_REG, @as(u8, 0x80));
|
||||
arch.addTestParams("inb", .{ SLAVE_STATUS_REG, @as(u8, 0x80) });
|
||||
|
||||
// Pre testing
|
||||
expectEqual(@as(u32, 0), spurious_irq_counter);
|
||||
|
|
@ -687,11 +687,11 @@ test "spuriousIrq spurious slave IRQ number spurious" {
|
|||
arch.initTest();
|
||||
defer arch.freeTest();
|
||||
|
||||
arch.addTestParams("outb", SLAVE_COMMAND_REG, @as(u8, 0x0B));
|
||||
arch.addTestParams("outb", .{ SLAVE_COMMAND_REG, @as(u8, 0x0B) });
|
||||
// Return 0x0 from readSlaveIsr() which will mean this was a spurious IRQ
|
||||
arch.addTestParams("inb", SLAVE_STATUS_REG, @as(u8, 0x0));
|
||||
arch.addTestParams("inb", .{ SLAVE_STATUS_REG, @as(u8, 0x0) });
|
||||
// A EOI will be sent for a spurious IRQ 15
|
||||
arch.addTestParams("outb", MASTER_COMMAND_REG, OCW2_END_OF_INTERRUPT);
|
||||
arch.addTestParams("outb", .{ MASTER_COMMAND_REG, OCW2_END_OF_INTERRUPT });
|
||||
|
||||
// Pre testing
|
||||
expectEqual(@as(u32, 0), spurious_irq_counter);
|
||||
|
|
@ -712,9 +712,9 @@ test "setMask master IRQ masked" {
|
|||
defer arch.freeTest();
|
||||
|
||||
// Going to assume all bits are masked out
|
||||
arch.addTestParams("inb", MASTER_DATA_REG, @as(u8, 0xFF));
|
||||
arch.addTestParams("inb", .{ MASTER_DATA_REG, @as(u8, 0xFF) });
|
||||
// Expect the 2nd bit to be set
|
||||
arch.addTestParams("outb", MASTER_DATA_REG, @as(u8, 0xFF));
|
||||
arch.addTestParams("outb", .{ MASTER_DATA_REG, @as(u8, 0xFF) });
|
||||
|
||||
setMask(1);
|
||||
}
|
||||
|
|
@ -725,9 +725,9 @@ test "setMask master IRQ unmasked" {
|
|||
defer arch.freeTest();
|
||||
|
||||
// IRQ already unmasked
|
||||
arch.addTestParams("inb", MASTER_DATA_REG, @as(u8, 0xFD));
|
||||
arch.addTestParams("inb", .{ MASTER_DATA_REG, @as(u8, 0xFD) });
|
||||
// Expect the 2nd bit to be set
|
||||
arch.addTestParams("outb", MASTER_DATA_REG, @as(u8, 0xFF));
|
||||
arch.addTestParams("outb", .{ MASTER_DATA_REG, @as(u8, 0xFF) });
|
||||
|
||||
setMask(1);
|
||||
}
|
||||
|
|
@ -738,9 +738,9 @@ test "clearMask master IRQ masked" {
|
|||
defer arch.freeTest();
|
||||
|
||||
// Going to assume all bits are masked out
|
||||
arch.addTestParams("inb", MASTER_DATA_REG, @as(u8, 0xFF));
|
||||
arch.addTestParams("inb", .{ MASTER_DATA_REG, @as(u8, 0xFF) });
|
||||
// Expect the 2nd bit to be clear
|
||||
arch.addTestParams("outb", MASTER_DATA_REG, @as(u8, 0xFD));
|
||||
arch.addTestParams("outb", .{ MASTER_DATA_REG, @as(u8, 0xFD) });
|
||||
|
||||
clearMask(1);
|
||||
}
|
||||
|
|
@ -751,9 +751,9 @@ test "clearMask master IRQ unmasked" {
|
|||
defer arch.freeTest();
|
||||
|
||||
// IRQ already unmasked
|
||||
arch.addTestParams("inb", MASTER_DATA_REG, @as(u8, 0xFD));
|
||||
arch.addTestParams("inb", .{ MASTER_DATA_REG, @as(u8, 0xFD) });
|
||||
// Expect the 2nd bit to still be clear
|
||||
arch.addTestParams("outb", MASTER_DATA_REG, @as(u8, 0xFD));
|
||||
arch.addTestParams("outb", .{ MASTER_DATA_REG, @as(u8, 0xFD) });
|
||||
|
||||
clearMask(1);
|
||||
}
|
||||
|
|
@ -764,8 +764,7 @@ test "init" {
|
|||
defer arch.freeTest();
|
||||
|
||||
// Just a long list of OUT instructions setting up the PIC
|
||||
arch.addTestParams(
|
||||
"outb",
|
||||
arch.addTestParams("outb", .{
|
||||
MASTER_COMMAND_REG,
|
||||
ICW1_INITIALISATION | ICW1_EXPECT_ICW4,
|
||||
SLAVE_COMMAND_REG,
|
||||
|
|
@ -786,7 +785,7 @@ test "init" {
|
|||
@as(u8, 0xFF),
|
||||
SLAVE_DATA_REG,
|
||||
@as(u8, 0xFF),
|
||||
);
|
||||
});
|
||||
|
||||
init();
|
||||
}
|
||||
|
|
@ -796,14 +795,14 @@ test "init" {
|
|||
///
|
||||
fn rt_picAllMasked() void {
|
||||
if (readDataMaster() != 0xFF) {
|
||||
panic(@errorReturnTrace(), "Master masks are not set, found: {}\n", readDataMaster());
|
||||
panic(@errorReturnTrace(), "Master masks are not set, found: {}\n", .{readDataMaster()});
|
||||
}
|
||||
|
||||
if (readDataSlave() != 0xFF) {
|
||||
panic(@errorReturnTrace(), "Slave masks are not set, found: {}\n", readDataSlave());
|
||||
panic(@errorReturnTrace(), "Slave masks are not set, found: {}\n", .{readDataSlave()});
|
||||
}
|
||||
|
||||
log.logInfo("PIC: Tested masking\n");
|
||||
log.logInfo("PIC: Tested masking\n", .{});
|
||||
}
|
||||
|
||||
///
|
||||
|
|
|
|||
|
|
@ -370,26 +370,26 @@ pub fn getFrequency() u32 {
|
|||
/// Initialise the PIT with a handler to IRQ 0.
|
||||
///
|
||||
pub fn init() void {
|
||||
log.logInfo("Init pit\n");
|
||||
log.logInfo("Init pit\n", .{});
|
||||
// Set up counter 0 at 10000hz in a square wave mode counting in binary
|
||||
const freq: u32 = 10000;
|
||||
setupCounter(CounterSelect.Counter0, freq, OCW_MODE_SQUARE_WAVE_GENERATOR | OCW_BINARY_COUNT_BINARY) catch |e| {
|
||||
panic(@errorReturnTrace(), "Invalid frequency: {}\n", freq);
|
||||
panic(@errorReturnTrace(), "Invalid frequency: {}\n", .{freq});
|
||||
};
|
||||
|
||||
log.logDebug("Set frequency at: {}Hz, real frequency: {}Hz\n", freq, getFrequency());
|
||||
log.logDebug("Set frequency at: {}Hz, real frequency: {}Hz\n", .{ freq, getFrequency() });
|
||||
|
||||
// Installs 'pitHandler' to IRQ0 (pic.IRQ_PIT)
|
||||
irq.registerIrq(pic.IRQ_PIT, pitHandler) catch |err| switch (err) {
|
||||
error.IrqExists => {
|
||||
panic(@errorReturnTrace(), "IRQ for PIT, IRQ number: {} exists", pic.IRQ_PIT);
|
||||
panic(@errorReturnTrace(), "IRQ for PIT, IRQ number: {} exists", .{pic.IRQ_PIT});
|
||||
},
|
||||
error.InvalidIrq => {
|
||||
panic(@errorReturnTrace(), "IRQ for PIT, IRQ number: {} is invalid", pic.IRQ_PIT);
|
||||
panic(@errorReturnTrace(), "IRQ for PIT, IRQ number: {} is invalid", .{pic.IRQ_PIT});
|
||||
},
|
||||
};
|
||||
|
||||
log.logInfo("Done\n");
|
||||
log.logInfo("Done\n", .{});
|
||||
|
||||
if (build_options.rt_test) runtimeTests();
|
||||
}
|
||||
|
|
@ -400,7 +400,7 @@ test "sendCommand" {
|
|||
|
||||
const cmd: u8 = 10;
|
||||
|
||||
arch.addTestParams("outb", COMMAND_REGISTER, cmd);
|
||||
arch.addTestParams("outb", .{ COMMAND_REGISTER, cmd });
|
||||
|
||||
sendCommand(cmd);
|
||||
}
|
||||
|
|
@ -411,8 +411,8 @@ test "readBackCommand" {
|
|||
|
||||
const cmd: u8 = 0xC2;
|
||||
|
||||
arch.addTestParams("outb", COMMAND_REGISTER, cmd);
|
||||
arch.addTestParams("inb", COUNTER_0_REGISTER, @as(u8, 0x20));
|
||||
arch.addTestParams("outb", .{ COMMAND_REGISTER, cmd });
|
||||
arch.addTestParams("inb", .{ COUNTER_0_REGISTER, @as(u8, 0x20) });
|
||||
|
||||
const actual = readBackCommand(CounterSelect.Counter0);
|
||||
|
||||
|
|
@ -425,7 +425,7 @@ test "sendDataToCounter" {
|
|||
|
||||
const data: u8 = 10;
|
||||
|
||||
arch.addTestParams("outb", COUNTER_0_REGISTER, data);
|
||||
arch.addTestParams("outb", .{ COUNTER_0_REGISTER, data });
|
||||
|
||||
sendDataToCounter(CounterSelect.Counter0, data);
|
||||
}
|
||||
|
|
@ -519,7 +519,7 @@ test "setupCounter normal frequency" {
|
|||
const mode = OCW_MODE_SQUARE_WAVE_GENERATOR | OCW_BINARY_COUNT_BINARY;
|
||||
const command = mode | OCW_READ_LOAD_DATA | counter.getCounterOCW();
|
||||
|
||||
arch.addTestParams("outb", COMMAND_REGISTER, command, port, @truncate(u8, expected_reload_value), port, @truncate(u8, expected_reload_value >> 8));
|
||||
arch.addTestParams("outb", .{ COMMAND_REGISTER, command, port, @truncate(u8, expected_reload_value), port, @truncate(u8, expected_reload_value >> 8) });
|
||||
|
||||
setupCounter(counter, freq, mode) catch unreachable;
|
||||
|
||||
|
|
@ -551,10 +551,10 @@ fn rt_waitTicks() void {
|
|||
const difference = getTicks() - waiting;
|
||||
|
||||
if (previous_count + epsilon < difference or previous_count > difference + epsilon) {
|
||||
panic(@errorReturnTrace(), "Waiting failed. difference: {}, previous_count: {}. Epsilon: {}\n", difference, previous_count, epsilon);
|
||||
panic(@errorReturnTrace(), "Waiting failed. difference: {}, previous_count: {}. Epsilon: {}\n", .{ difference, previous_count, epsilon });
|
||||
}
|
||||
|
||||
log.logInfo("PIT: Tested wait ticks\n");
|
||||
log.logInfo("PIT: Tested wait ticks\n", .{});
|
||||
}
|
||||
|
||||
///
|
||||
|
|
@ -575,10 +575,10 @@ fn rt_waitTicks2() void {
|
|||
const difference = getTicks() + 15 - waiting;
|
||||
|
||||
if (previous_count + epsilon < difference or previous_count > difference + epsilon) {
|
||||
panic(@errorReturnTrace(), "Waiting failed. difference: {}, previous_count: {}. Epsilon: {}\n", difference, previous_count, epsilon);
|
||||
panic(@errorReturnTrace(), "Waiting failed. difference: {}, previous_count: {}. Epsilon: {}\n", .{ difference, previous_count, epsilon });
|
||||
}
|
||||
|
||||
log.logInfo("PIT: Tested wait ticks 2\n");
|
||||
log.logInfo("PIT: Tested wait ticks 2\n", .{});
|
||||
|
||||
// Reset ticks
|
||||
ticks = 0;
|
||||
|
|
@ -593,16 +593,14 @@ fn rt_initCounter_0() void {
|
|||
const expected_hz: u32 = 10027;
|
||||
|
||||
if (time_ns != expected_ns or time_under_1_ns != expected_ps or getFrequency() != expected_hz) {
|
||||
panic(
|
||||
@errorReturnTrace(),
|
||||
"Frequency not set properly. Hz: {}!={}, ns: {}!={}, ps: {}!= {}\n",
|
||||
panic(@errorReturnTrace(), "Frequency not set properly. Hz: {}!={}, ns: {}!={}, ps: {}!= {}\n", .{
|
||||
getFrequency(),
|
||||
expected_hz,
|
||||
time_ns,
|
||||
expected_ns,
|
||||
time_under_1_ns,
|
||||
expected_ps,
|
||||
);
|
||||
});
|
||||
}
|
||||
|
||||
var irq_exists = false;
|
||||
|
|
@ -613,22 +611,22 @@ fn rt_initCounter_0() void {
|
|||
irq_exists = true;
|
||||
},
|
||||
error.InvalidIrq => {
|
||||
panic(@errorReturnTrace(), "IRQ for PIT, IRQ number: {} is invalid", pic.IRQ_PIT);
|
||||
panic(@errorReturnTrace(), "IRQ for PIT, IRQ number: {} is invalid", .{pic.IRQ_PIT});
|
||||
},
|
||||
};
|
||||
|
||||
if (!irq_exists) {
|
||||
panic(@errorReturnTrace(), "IRQ for PIT doesn't exists\n");
|
||||
panic(@errorReturnTrace(), "IRQ for PIT doesn't exists\n", .{});
|
||||
}
|
||||
|
||||
const expected_mode = OCW_READ_LOAD_DATA | OCW_MODE_SQUARE_WAVE_GENERATOR | OCW_SELECT_COUNTER_0 | OCW_BINARY_COUNT_BINARY;
|
||||
const actual_mode = readBackCommand(CounterSelect.Counter0);
|
||||
|
||||
if (expected_mode != actual_mode) {
|
||||
panic(@errorReturnTrace(), "Operating mode don't not set properly. Found: {}, expecting: {}\n", actual_mode, expected_mode);
|
||||
panic(@errorReturnTrace(), "Operating mode don't not set properly. Found: {}, expecting: {}\n", .{ actual_mode, expected_mode });
|
||||
}
|
||||
|
||||
log.logInfo("PIT: Tested init\n");
|
||||
log.logInfo("PIT: Tested init\n", .{});
|
||||
}
|
||||
|
||||
///
|
||||
|
|
|
|||
|
|
@ -53,10 +53,10 @@ fn handle(ctx: *arch.InterruptContext) void {
|
|||
if (handlers[syscall]) |handler| {
|
||||
ctx.eax = handler(ctx, syscallArg(ctx, 0), syscallArg(ctx, 1), syscallArg(ctx, 2), syscallArg(ctx, 3), syscallArg(ctx, 4));
|
||||
} else {
|
||||
log.logWarning("Syscall {} triggered but not registered\n", syscall);
|
||||
log.logWarning("Syscall {} triggered but not registered\n", .{syscall});
|
||||
}
|
||||
} else {
|
||||
log.logWarning("Syscall {} is invalid\n", syscall);
|
||||
log.logWarning("Syscall {} is invalid\n", .{syscall});
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -237,9 +237,9 @@ inline fn syscallArg(ctx: *arch.InterruptContext, comptime arg_idx: u32) u32 {
|
|||
/// Initialise syscalls. Registers the isr associated with INTERRUPT.
|
||||
///
|
||||
pub fn init() void {
|
||||
log.logInfo("Init syscalls\n");
|
||||
log.logInfo("Init syscalls\n", .{});
|
||||
isr.registerIsr(INTERRUPT, handle) catch unreachable;
|
||||
log.logInfo("Done\n");
|
||||
log.logInfo("Done\n", .{});
|
||||
if (options.rt_test) runtimeTests();
|
||||
}
|
||||
|
||||
|
|
@ -294,20 +294,20 @@ fn runtimeTests() void {
|
|||
assert(testInt == 0);
|
||||
|
||||
if (syscall0(123) == 0 and testInt == 1)
|
||||
log.logInfo("Syscalls: Tested no args\n");
|
||||
log.logInfo("Syscalls: Tested no args\n", .{});
|
||||
|
||||
if (syscall1(124, 2) == 1 and testInt == 3)
|
||||
log.logInfo("Syscalls: Tested 1 arg\n");
|
||||
log.logInfo("Syscalls: Tested 1 arg\n", .{});
|
||||
|
||||
if (syscall2(125, 2, 3) == 2 and testInt == 8)
|
||||
log.logInfo("Syscalls: Tested 2 args\n");
|
||||
log.logInfo("Syscalls: Tested 2 args\n", .{});
|
||||
|
||||
if (syscall3(126, 2, 3, 4) == 3 and testInt == 17)
|
||||
log.logInfo("Syscalls: Tested 3 args\n");
|
||||
log.logInfo("Syscalls: Tested 3 args\n", .{});
|
||||
|
||||
if (syscall4(127, 2, 3, 4, 5) == 4 and testInt == 31)
|
||||
log.logInfo("Syscalls: Tested 4 args\n");
|
||||
log.logInfo("Syscalls: Tested 4 args\n", .{});
|
||||
|
||||
if (syscall5(128, 2, 3, 4, 5, 6) == 5 and testInt == 51)
|
||||
log.logInfo("Syscalls: Tested 5 args\n");
|
||||
log.logInfo("Syscalls: Tested 5 args\n", .{});
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue