Update code to work with zig master
This commit is contained in:
Sam Tebbs
parent
4b870d3a65
commit
91b2a61acf
26 changed files with 476 additions and 438 deletions
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@ -432,7 +432,7 @@ pub fn clearMask(irq_num: u8) void {
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/// by Intel up to 0x1F. So this will move the IRQs from 0x00-0x0F to 0x20-0x2F.
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///
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pub fn init() void {
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log.logInfo("Init pic\n");
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log.logInfo("Init pic\n", .{});
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// Initiate
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sendCommandMaster(ICW1_INITIALISATION | ICW1_EXPECT_ICW4);
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@ -454,7 +454,7 @@ pub fn init() void {
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sendDataMaster(0xFF);
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sendDataSlave(0xFF);
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log.logInfo("Done\n");
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log.logInfo("Done\n", .{});
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if (build_options.rt_test) runtimeTests();
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}
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@ -466,7 +466,7 @@ test "sendCommandMaster" {
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const cmd: u8 = 10;
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arch.addTestParams("outb", MASTER_COMMAND_REG, cmd);
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arch.addTestParams("outb", .{ MASTER_COMMAND_REG, cmd });
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sendCommandMaster(cmd);
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}
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@ -478,7 +478,7 @@ test "sendCommandSlave" {
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const cmd: u8 = 10;
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arch.addTestParams("outb", SLAVE_COMMAND_REG, cmd);
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arch.addTestParams("outb", .{ SLAVE_COMMAND_REG, cmd });
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sendCommandSlave(cmd);
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}
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@ -490,7 +490,7 @@ test "sendDataMaster" {
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const data: u8 = 10;
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arch.addTestParams("outb", MASTER_DATA_REG, data);
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arch.addTestParams("outb", .{ MASTER_DATA_REG, data });
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sendDataMaster(data);
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}
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@ -502,7 +502,7 @@ test "sendDataSlave" {
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const data: u8 = 10;
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arch.addTestParams("outb", SLAVE_DATA_REG, data);
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arch.addTestParams("outb", .{ SLAVE_DATA_REG, data });
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sendDataSlave(data);
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}
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@ -512,7 +512,7 @@ test "readDataMaster" {
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arch.initTest();
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defer arch.freeTest();
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arch.addTestParams("inb", MASTER_DATA_REG, @as(u8, 10));
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arch.addTestParams("inb", .{ MASTER_DATA_REG, @as(u8, 10) });
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expectEqual(@as(u8, 10), readDataMaster());
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}
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@ -522,7 +522,7 @@ test "readDataSlave" {
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arch.initTest();
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defer arch.freeTest();
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arch.addTestParams("inb", SLAVE_DATA_REG, @as(u8, 10));
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arch.addTestParams("inb", .{ SLAVE_DATA_REG, @as(u8, 10) });
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expectEqual(@as(u8, 10), readDataSlave());
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}
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@ -532,8 +532,8 @@ test "readMasterIrr" {
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arch.initTest();
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defer arch.freeTest();
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arch.addTestParams("outb", MASTER_COMMAND_REG, @as(u8, 0x0A));
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arch.addTestParams("inb", MASTER_STATUS_REG, @as(u8, 10));
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arch.addTestParams("outb", .{ MASTER_COMMAND_REG, @as(u8, 0x0A) });
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arch.addTestParams("inb", .{ MASTER_STATUS_REG, @as(u8, 10) });
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expectEqual(@as(u8, 10), readMasterIrr());
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}
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@ -543,8 +543,8 @@ test "readSlaveIrr" {
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arch.initTest();
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defer arch.freeTest();
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arch.addTestParams("outb", SLAVE_COMMAND_REG, @as(u8, 0x0A));
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arch.addTestParams("inb", SLAVE_STATUS_REG, @as(u8, 10));
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arch.addTestParams("outb", .{ SLAVE_COMMAND_REG, @as(u8, 0x0A) });
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arch.addTestParams("inb", .{ SLAVE_STATUS_REG, @as(u8, 10) });
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expectEqual(@as(u8, 10), readSlaveIrr());
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}
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@ -554,8 +554,8 @@ test "readMasterIsr" {
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arch.initTest();
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defer arch.freeTest();
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arch.addTestParams("outb", MASTER_COMMAND_REG, @as(u8, 0x0B));
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arch.addTestParams("inb", MASTER_STATUS_REG, @as(u8, 10));
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arch.addTestParams("outb", .{ MASTER_COMMAND_REG, @as(u8, 0x0B) });
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arch.addTestParams("inb", .{ MASTER_STATUS_REG, @as(u8, 10) });
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expectEqual(@as(u8, 10), readMasterIsr());
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}
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@ -565,8 +565,8 @@ test "readSlaveIsr" {
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arch.initTest();
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defer arch.freeTest();
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arch.addTestParams("outb", SLAVE_COMMAND_REG, @as(u8, 0x0B));
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arch.addTestParams("inb", SLAVE_STATUS_REG, @as(u8, 10));
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arch.addTestParams("outb", .{ SLAVE_COMMAND_REG, @as(u8, 0x0B) });
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arch.addTestParams("inb", .{ SLAVE_STATUS_REG, @as(u8, 10) });
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expectEqual(@as(u8, 10), readSlaveIsr());
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}
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@ -578,7 +578,7 @@ test "sendEndOfInterrupt master only" {
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var i: u8 = 0;
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while (i < 8) : (i += 1) {
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arch.addTestParams("outb", MASTER_COMMAND_REG, OCW2_END_OF_INTERRUPT);
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arch.addTestParams("outb", .{ MASTER_COMMAND_REG, OCW2_END_OF_INTERRUPT });
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sendEndOfInterrupt(i);
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}
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@ -591,8 +591,8 @@ test "sendEndOfInterrupt master and slave" {
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var i: u8 = 8;
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while (i < 16) : (i += 1) {
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arch.addTestParams("outb", SLAVE_COMMAND_REG, OCW2_END_OF_INTERRUPT);
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arch.addTestParams("outb", MASTER_COMMAND_REG, OCW2_END_OF_INTERRUPT);
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arch.addTestParams("outb", .{ SLAVE_COMMAND_REG, OCW2_END_OF_INTERRUPT });
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arch.addTestParams("outb", .{ MASTER_COMMAND_REG, OCW2_END_OF_INTERRUPT });
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sendEndOfInterrupt(i);
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}
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@ -621,9 +621,9 @@ test "spuriousIrq spurious master IRQ number not spurious" {
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arch.initTest();
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defer arch.freeTest();
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arch.addTestParams("outb", MASTER_COMMAND_REG, @as(u8, 0x0B));
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arch.addTestParams("outb", .{ MASTER_COMMAND_REG, @as(u8, 0x0B) });
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// Return 0x80 from readMasterIsr() which will mean this was a real IRQ
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arch.addTestParams("inb", MASTER_STATUS_REG, @as(u8, 0x80));
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arch.addTestParams("inb", .{ MASTER_STATUS_REG, @as(u8, 0x80) });
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// Pre testing
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expectEqual(@as(u32, 0), spurious_irq_counter);
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@ -643,9 +643,9 @@ test "spuriousIrq spurious master IRQ number spurious" {
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arch.initTest();
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defer arch.freeTest();
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arch.addTestParams("outb", MASTER_COMMAND_REG, @as(u8, 0x0B));
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arch.addTestParams("outb", .{ MASTER_COMMAND_REG, @as(u8, 0x0B) });
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// Return 0x0 from readMasterIsr() which will mean this was a spurious IRQ
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arch.addTestParams("inb", MASTER_STATUS_REG, @as(u8, 0x0));
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arch.addTestParams("inb", .{ MASTER_STATUS_REG, @as(u8, 0x0) });
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// Pre testing
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expectEqual(@as(u32, 0), spurious_irq_counter);
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@ -665,9 +665,9 @@ test "spuriousIrq spurious slave IRQ number not spurious" {
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arch.initTest();
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defer arch.freeTest();
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arch.addTestParams("outb", SLAVE_COMMAND_REG, @as(u8, 0x0B));
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arch.addTestParams("outb", .{ SLAVE_COMMAND_REG, @as(u8, 0x0B) });
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// Return 0x80 from readSlaveIsr() which will mean this was a real IRQ
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arch.addTestParams("inb", SLAVE_STATUS_REG, @as(u8, 0x80));
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arch.addTestParams("inb", .{ SLAVE_STATUS_REG, @as(u8, 0x80) });
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// Pre testing
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expectEqual(@as(u32, 0), spurious_irq_counter);
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@ -687,11 +687,11 @@ test "spuriousIrq spurious slave IRQ number spurious" {
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arch.initTest();
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defer arch.freeTest();
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arch.addTestParams("outb", SLAVE_COMMAND_REG, @as(u8, 0x0B));
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arch.addTestParams("outb", .{ SLAVE_COMMAND_REG, @as(u8, 0x0B) });
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// Return 0x0 from readSlaveIsr() which will mean this was a spurious IRQ
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arch.addTestParams("inb", SLAVE_STATUS_REG, @as(u8, 0x0));
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arch.addTestParams("inb", .{ SLAVE_STATUS_REG, @as(u8, 0x0) });
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// A EOI will be sent for a spurious IRQ 15
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arch.addTestParams("outb", MASTER_COMMAND_REG, OCW2_END_OF_INTERRUPT);
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arch.addTestParams("outb", .{ MASTER_COMMAND_REG, OCW2_END_OF_INTERRUPT });
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// Pre testing
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expectEqual(@as(u32, 0), spurious_irq_counter);
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@ -712,9 +712,9 @@ test "setMask master IRQ masked" {
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defer arch.freeTest();
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// Going to assume all bits are masked out
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arch.addTestParams("inb", MASTER_DATA_REG, @as(u8, 0xFF));
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arch.addTestParams("inb", .{ MASTER_DATA_REG, @as(u8, 0xFF) });
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// Expect the 2nd bit to be set
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arch.addTestParams("outb", MASTER_DATA_REG, @as(u8, 0xFF));
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arch.addTestParams("outb", .{ MASTER_DATA_REG, @as(u8, 0xFF) });
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setMask(1);
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}
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@ -725,9 +725,9 @@ test "setMask master IRQ unmasked" {
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defer arch.freeTest();
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// IRQ already unmasked
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arch.addTestParams("inb", MASTER_DATA_REG, @as(u8, 0xFD));
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arch.addTestParams("inb", .{ MASTER_DATA_REG, @as(u8, 0xFD) });
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// Expect the 2nd bit to be set
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arch.addTestParams("outb", MASTER_DATA_REG, @as(u8, 0xFF));
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arch.addTestParams("outb", .{ MASTER_DATA_REG, @as(u8, 0xFF) });
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setMask(1);
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}
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@ -738,9 +738,9 @@ test "clearMask master IRQ masked" {
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defer arch.freeTest();
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// Going to assume all bits are masked out
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arch.addTestParams("inb", MASTER_DATA_REG, @as(u8, 0xFF));
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arch.addTestParams("inb", .{ MASTER_DATA_REG, @as(u8, 0xFF) });
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// Expect the 2nd bit to be clear
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arch.addTestParams("outb", MASTER_DATA_REG, @as(u8, 0xFD));
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arch.addTestParams("outb", .{ MASTER_DATA_REG, @as(u8, 0xFD) });
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clearMask(1);
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}
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@ -751,9 +751,9 @@ test "clearMask master IRQ unmasked" {
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defer arch.freeTest();
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// IRQ already unmasked
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arch.addTestParams("inb", MASTER_DATA_REG, @as(u8, 0xFD));
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arch.addTestParams("inb", .{ MASTER_DATA_REG, @as(u8, 0xFD) });
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// Expect the 2nd bit to still be clear
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arch.addTestParams("outb", MASTER_DATA_REG, @as(u8, 0xFD));
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arch.addTestParams("outb", .{ MASTER_DATA_REG, @as(u8, 0xFD) });
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clearMask(1);
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}
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@ -764,8 +764,7 @@ test "init" {
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defer arch.freeTest();
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// Just a long list of OUT instructions setting up the PIC
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arch.addTestParams(
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"outb",
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arch.addTestParams("outb", .{
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MASTER_COMMAND_REG,
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ICW1_INITIALISATION | ICW1_EXPECT_ICW4,
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SLAVE_COMMAND_REG,
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@ -786,7 +785,7 @@ test "init" {
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@as(u8, 0xFF),
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SLAVE_DATA_REG,
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@as(u8, 0xFF),
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);
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});
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init();
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}
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@ -796,14 +795,14 @@ test "init" {
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///
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fn rt_picAllMasked() void {
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if (readDataMaster() != 0xFF) {
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panic(@errorReturnTrace(), "Master masks are not set, found: {}\n", readDataMaster());
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panic(@errorReturnTrace(), "Master masks are not set, found: {}\n", .{readDataMaster()});
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}
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if (readDataSlave() != 0xFF) {
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panic(@errorReturnTrace(), "Slave masks are not set, found: {}\n", readDataSlave());
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panic(@errorReturnTrace(), "Slave masks are not set, found: {}\n", .{readDataSlave()});
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}
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log.logInfo("PIC: Tested masking\n");
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log.logInfo("PIC: Tested masking\n", .{});
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}
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///
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