2 commits

Author	SHA1	Message	Date
DrDeano	1f97a5c6c8	Updating to zig master ... Added cpu model Moved logging to defer done log Moved mem.init to bottom Updated again to new zig master	2020-04-12 22:26:34 +01:00
DrDeano	7ab180f622	Added RTC ... Added I/O waits to PIC remapping Added fmt step to build When building will format all the code to the standard Fixed cascading interrupts Re-named to selectAnd*Register. Moved switching on registers into emun Removed build fmt step	2020-01-15 19:50:47 +00:00