31 lines
855 B
VHDL
31 lines
855 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity Destination_Block is
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Port (
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regEna : in STD_LOGIC; -- Input register enable signal
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dest : in STD_LOGIC; -- Input destination select signal (0 or 1)
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ena0 : out STD_LOGIC; -- Output enable signal for register 0
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ena1 : out STD_LOGIC -- Output enable signal for register 1
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);
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end Destination_Block;
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architecture Behavioral of Destination_Block is
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begin
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process (regEna, dest)
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begin
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-- Initialize outputs to default values
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ena0 <= '0';
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ena1 <= '0';
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-- Enable the selected destination register based on dest signal
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if regEna = '1' then
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if dest = '0' then
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ena0 <= '1';
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else
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ena1 <= '1';
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end if;
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end if;
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end process;
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end Behavioral;
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