71 lines
2.8 KiB
VHDL
71 lines
2.8 KiB
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity Instruction_Decoder is
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Port (
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opcode : in STD_LOGIC_VECTOR(3 downto 0); -- Input opcode
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z_flag : in STD_LOGIC; -- Input zero flag
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IntDone : in STD_LOGIC; -- Input interrupt done signal
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stackOp : out STD_LOGIC; -- Output stack operation signal
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addrSrc : out STD_LOGIC_VECTOR(1 downto 0); -- Output address source select
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ALUOp : out STD_LOGIC_VECTOR(2 downto 0); -- Output ALU operation select
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ALUSrc : out STD_LOGIC; -- Output ALU source select
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regEna : out STD_LOGIC; -- Output register enable signal
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OutEna : out STD_LOGIC -- Output data output enable signal
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);
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end Instruction_Decoder;
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architecture Behavioral of Instruction_Decoder is
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begin
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process (opcode, z_flag, IntDone)
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begin
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-- Initialize outputs to default values
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stackOp <= '0';
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addrSrc <= "00";
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ALUOp <= "000";
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ALUSrc <= '0';
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regEna <= '0';
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OutEna <= '0';
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-- Decode instructions based on opcode [12:9]
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case opcode is
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when "0000" =>
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stackOp <= '1'; -- Instruction 0000: Push onto stack
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when "0001" =>
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stackOp <= '0'; -- Instruction 0001: Pop from stack
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when "0010" =>
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addrSrc <= "01"; -- Instruction 0010: Load address from register
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regEna <= '1';
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OutEna <= '1';
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when "0011" =>
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ALUOp <= "001"; -- Instruction 0011: ALU operation ADD
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ALUSrc <= '1';
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OutEna <= '1';
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when "0100" =>
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ALUOp <= "010"; -- Instruction 0100: ALU operation SUB
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ALUSrc <= '1';
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OutEna <= '1';
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when "0101" =>
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ALUOp <= "011"; -- Instruction 0101: ALU operation AND
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ALUSrc <= '1';
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OutEna <= '1';
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when "0110" =>
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ALUOp <= "100"; -- Instruction 0110: ALU operation OR
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ALUSrc <= '1';
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OutEna <= '1';
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when "0111" =>
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ALUOp <= "101"; -- Instruction 0111: ALU operation XOR
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ALUSrc <= '1';
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OutEna <= '1';
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when "1000" =>
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if z_flag = '1' then
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addrSrc <= "10"; -- Instruction 1000: Jump if Zero (JZ)
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else
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addrSrc <= "11"; -- Instruction 1000: Jump if Not Zero (JNZ)
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end if;
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when others =>
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null; -- Other instructions not specified, outputs remain at default values
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end case;
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end process;
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end Behavioral;
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