32 lines
1 KiB
VHDL
32 lines
1 KiB
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity Program_Counter is
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Port (
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clk : in STD_LOGIC; -- Clock input
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rst : in STD_LOGIC; -- Reset input
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increment : in STD_LOGIC; -- Signal to increment the PC
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addr : out STD_LOGIC_VECTOR(7 downto 0) -- Program counter output
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);
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end Program_Counter;
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architecture Behavioral of Program_Counter is
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signal pc_reg : STD_LOGIC_VECTOR(7 downto 0) := "00000000"; -- Initial value for the program counter
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begin
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process (clk, rst, increment)
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begin
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if rst = '1' then
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pc_reg <= "00000000"; -- Reset the program counter to 0
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elsif rising_edge(clk) then
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if increment = '1' then
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pc_reg <= pc_reg + 1; -- Increment the program counter
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end if;
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end if;
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end process;
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addr <= pc_reg; -- Output the program counter value
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end Behavioral;
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