workreg_mplex/stack.vhdl

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VHDL
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2023-11-08 09:35:43 +01:00
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Stack is
Port (
push : in STD_LOGIC; -- Signal to push data onto the stack
pop : in STD_LOGIC; -- Signal to pop data from the stack
data_in : in STD_LOGIC_VECTOR(7 downto 0); -- Input data to be pushed onto the stack
data_out: out STD_LOGIC_VECTOR(7 downto 0) -- Data popped from the stack
);
end Stack;
architecture Behavioral of Stack is
type Stack_Type is array (0 to 7) of STD_LOGIC_VECTOR(7 downto 0);
signal stack_memory : Stack_Type;
signal stack_pointer: STD_LOGIC_VECTOR(2 downto 0) := "000"; -- Initial stack pointer
begin
process (push, pop, data_in)
begin
if push = '1' then
if stack_pointer = "111" then
-- Stack is full, no more pushing allowed
report "Stack Overflow";
else
stack_memory(to_integer(unsigned(stack_pointer))) <= data_in;
stack_pointer <= stack_pointer + 1;
end if;
elsif pop = '1' then
if stack_pointer = "000" then
-- Stack is empty, no more popping allowed
report "Stack Underflow";
else
stack_pointer <= stack_pointer - 1;
end if;
end if;
end process;
data_out <= stack_memory(to_integer(unsigned(stack_pointer))); -- Output the data from the stack
end Behavioral;