41 lines
1.4 KiB
VHDL
41 lines
1.4 KiB
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity Stack is
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Port (
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push : in STD_LOGIC; -- Signal to push data onto the stack
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pop : in STD_LOGIC; -- Signal to pop data from the stack
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data_in : in STD_LOGIC_VECTOR(7 downto 0); -- Input data to be pushed onto the stack
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data_out: out STD_LOGIC_VECTOR(7 downto 0) -- Data popped from the stack
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);
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end Stack;
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architecture Behavioral of Stack is
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type Stack_Type is array (0 to 7) of STD_LOGIC_VECTOR(7 downto 0);
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signal stack_memory : Stack_Type;
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signal stack_pointer: STD_LOGIC_VECTOR(2 downto 0) := "000"; -- Initial stack pointer
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begin
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process (push, pop, data_in)
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begin
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if push = '1' then
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if stack_pointer = "111" then
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-- Stack is full, no more pushing allowed
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report "Stack Overflow";
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else
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stack_memory(to_integer(unsigned(stack_pointer))) <= data_in;
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stack_pointer <= stack_pointer + 1;
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end if;
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elsif pop = '1' then
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if stack_pointer = "000" then
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-- Stack is empty, no more popping allowed
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report "Stack Underflow";
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else
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stack_pointer <= stack_pointer - 1;
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end if;
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end if;
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end process;
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data_out <= stack_memory(to_integer(unsigned(stack_pointer))); -- Output the data from the stack
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end Behavioral;
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