46 lines
1.1 KiB
VHDL
46 lines
1.1 KiB
VHDL
|
library IEEE;
|
||
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
||
|
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
||
|
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||
|
|
|
||
|
|
entity Multiplexer_8to1 is
|
||
|
|
Port (
|
||
|
|
Data_0 : in STD_LOGIC;
|
||
|
|
Data_1 : in STD_LOGIC;
|
||
|
|
Data_2 : in STD_LOGIC;
|
||
|
|
Data_3 : in STD_LOGIC;
|
||
|
|
Data_4 : in STD_LOGIC;
|
||
|
|
Data_5 : in STD_LOGIC;
|
||
|
|
Data_6 : in STD_LOGIC;
|
||
|
|
Data_7 : in STD_LOGIC;
|
||
|
|
Sel : in STD_LOGIC_VECTOR(2 downto 0);
|
||
|
|
Y : out STD_LOGIC
|
||
|
|
);
|
||
|
|
end Multiplexer_8to1;
|
||
|
|
|
||
|
|
architecture Behavioral of Multiplexer_8to1 is
|
||
|
|
begin
|
||
|
|
process(Sel, Data_0, Data_1, Data_2, Data_3, Data_4, Data_5, Data_6, Data_7)
|
||
|
|
begin
|
||
|
|
case Sel is
|
||
|
|
when "000" =>
|
||
|
|
Y <= Data_0;
|
||
|
|
when "001" =>
|
||
|
|
Y <= Data_1;
|
||
|
|
when "010" =>
|
||
|
|
Y <= Data_2;
|
||
|
|
when "011" =>
|
||
|
|
Y <= Data_3;
|
||
|
|
when "100" =>
|
||
|
|
Y <= Data_4;
|
||
|
|
when "101" =>
|
||
|
|
Y <= Data_5;
|
||
|
|
when "110" =>
|
||
|
|
Y <= Data_6;
|
||
|
|
when others =>
|
||
|
|
Y <= Data_7;
|
||
|
|
end case;
|
||
|
|
end process;
|
||
|
|
end Behavioral;
|
||
|
|
|