70 lines
1.8 KiB
VHDL
70 lines
1.8 KiB
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity Work_Register_Block is
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Port (
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save_wreg : in STD_LOGIC;
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restore_wreg: in STD_LOGIC;
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D : in STD_LOGIC_VECTOR(7 downto 0);
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ena : in STD_LOGIC;
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clk : in STD_LOGIC;
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rst : in STD_LOGIC;
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Q : out STD_LOGIC_VECTOR(7 downto 0)
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);
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end Work_Register_Block;
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architecture Behavioral of Work_Register_Block is
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signal reg1_out : STD_LOGIC_VECTOR(7 downto 0);
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signal reg2_out : STD_LOGIC_VECTOR(7 downto 0);
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signal mux_sel : STD_LOGIC_VECTOR(2 downto 0);
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component Multiplexer_8to1 is
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Port (
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Data_0 : in STD_LOGIC_VECTOR(7 downto 0);
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Data_1 : in STD_LOGIC_VECTOR(7 downto 0);
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Sel : in STD_LOGIC_VECTOR(2 downto 0);
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Y : out STD_LOGIC_VECTOR(7 downto 0)
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);
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end component;
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component Register_8bit is
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Port (
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D : in STD_LOGIC_VECTOR(7 downto 0);
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ena : in STD_LOGIC;
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clk : in STD_LOGIC;
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rst : in STD_LOGIC;
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Q : out STD_LOGIC_VECTOR(7 downto 0)
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);
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end component;
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begin
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mux_sel <= "000" when save_wreg = '1' else "001";
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reg1_out <= D when save_wreg = '1' else reg2_out;
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Mux1: Multiplexer_8to1
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port map (
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Data_0 => reg2_out,
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Data_1 => D,
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Sel => mux_sel,
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Y => reg1_out
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);
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Register1: Register_8bit
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port map (
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D => reg1_out,
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ena => ena,
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clk => clk,
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rst => rst,
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Q => reg2_out
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);
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Register2: Register_8bit
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port map (
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D => reg2_out,
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ena => restore_wreg,
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clk => clk,
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rst => rst,
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Q => Q
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);
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end Behavioral;
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