library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ALU is
    Port (
        A, B    : in STD_LOGIC_VECTOR(7 downto 0);  -- Input operands A and B
        ALUOp   : in STD_LOGIC_VECTOR(2 downto 0);  -- ALU operation code
        ALUSrc  : in STD_LOGIC;                     -- Select between B and an immediate value
        result  : out STD_LOGIC_VECTOR(7 downto 0)  -- Output result
    );
end ALU;

architecture Behavioral of ALU is
begin
    process (A, B, ALUOp, ALUSrc)
        variable temp_result : STD_LOGIC_VECTOR(7 downto 0);
    begin
        -- Initialize temp_result to zero
        temp_result := (others => '0');

        -- Perform ALU operations based on ALUOp
        case ALUOp is
            when "000" =>
                if ALUSrc = '1' then
                    temp_result := A + B;  -- ADD operation
                else
                    temp_result := A + (others => '1');  -- ADD with immediate value
                end if;
            when "001" =>
                if ALUSrc = '1' then
                    temp_result := A - B;  -- SUB operation
                else
                    temp_result := A - (others => '1');  -- SUB with immediate value
                end if;
            when "010" =>
                temp_result := A AND B;  -- AND operation
            when "011" =>
                temp_result := A OR B;   -- OR operation
            when "100" =>
                temp_result := A XOR B;  -- XOR operation
            when "101" =>
                -- You can add more operations here as needed
                -- temp_result := ...;

            when others =>
                -- Handle undefined or unsupported operations
                temp_result := (others => '0');
        end case;

        result <= temp_result;  -- Output the result
    end process;
end Behavioral;