library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Work_Register_Block is Port ( save_wreg : in STD_LOGIC; restore_wreg: in STD_LOGIC; D : in STD_LOGIC_VECTOR(7 downto 0); ena : in STD_LOGIC; clk : in STD_LOGIC; rst : in STD_LOGIC; Q : out STD_LOGIC_VECTOR(7 downto 0) ); end Work_Register_Block; architecture Behavioral of Work_Register_Block is signal reg1_out : STD_LOGIC_VECTOR(7 downto 0); signal reg2_out : STD_LOGIC_VECTOR(7 downto 0); signal mux_sel : STD_LOGIC_VECTOR(2 downto 0); component Multiplexer_8to1 is Port ( Data_0 : in STD_LOGIC_VECTOR(7 downto 0); Data_1 : in STD_LOGIC_VECTOR(7 downto 0); Sel : in STD_LOGIC_VECTOR(2 downto 0); Y : out STD_LOGIC_VECTOR(7 downto 0) ); end component; component Register_8bit is Port ( D : in STD_LOGIC_VECTOR(7 downto 0); ena : in STD_LOGIC; clk : in STD_LOGIC; rst : in STD_LOGIC; Q : out STD_LOGIC_VECTOR(7 downto 0) ); end component; begin mux_sel <= "000" when save_wreg = '1' else "001"; reg1_out <= D when save_wreg = '1' else reg2_out; Mux1: Multiplexer_8to1 port map ( Data_0 => reg2_out, Data_1 => D, Sel => mux_sel, Y => reg1_out ); Register1: Register_8bit port map ( D => reg1_out, ena => ena, clk => clk, rst => rst, Q => reg2_out ); Register2: Register_8bit port map ( D => reg2_out, ena => restore_wreg, clk => clk, rst => rst, Q => Q ); end Behavioral;