library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Destination_Block is
    Port (
        regEna : in STD_LOGIC;  -- Input register enable signal
        dest   : in STD_LOGIC;  -- Input destination select signal (0 or 1)
        ena0   : out STD_LOGIC; -- Output enable signal for register 0
        ena1   : out STD_LOGIC  -- Output enable signal for register 1
    );
end Destination_Block;

architecture Behavioral of Destination_Block is
begin
    process (regEna, dest)
    begin
        -- Initialize outputs to default values
        ena0 <= '0';
        ena1 <= '0';

        -- Enable the selected destination register based on dest signal
        if regEna = '1' then
            if dest = '0' then
                ena0 <= '1';
            else
                ena1 <= '1';
            end if;
        end if;
    end process;
end Behavioral;