library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Multiplexer_8to1 is
    Port (
        Data_0 : in STD_LOGIC_VECTOR(7 downto 0);
        Data_1 : in STD_LOGIC_VECTOR(7 downto 0);
        Sel    : in STD_LOGIC_VECTOR(2 downto 0);
        Y      : out STD_LOGIC_VECTOR(7 downto 0)
    );
end Multiplexer_8to1;

architecture Behavioral of Multiplexer_8to1 is
begin
    process(Data_0, Data_1, Sel)
    begin
        case Sel is
            when "000" =>
                Y <= Data_0;
            when others =>
                Y <= Data_1;
        end case;
    end process;
end Behavioral;