library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Program_Counter is
    Port (
        clk     : in STD_LOGIC;                 -- Clock input
        rst     : in STD_LOGIC;                 -- Reset input
        increment : in STD_LOGIC;               -- Signal to increment the PC
        addr    : out STD_LOGIC_VECTOR(7 downto 0)  -- Program counter output
    );
end Program_Counter;

architecture Behavioral of Program_Counter is
    signal pc_reg : STD_LOGIC_VECTOR(7 downto 0) := "00000000";  -- Initial value for the program counter

begin
    process (clk, rst, increment)
    begin
        if rst = '1' then
            pc_reg <= "00000000";  -- Reset the program counter to 0
        elsif rising_edge(clk) then
            if increment = '1' then
                pc_reg <= pc_reg + 1;  -- Increment the program counter
            end if;
        end if;
    end process;

    addr <= pc_reg;  -- Output the program counter value
end Behavioral;