library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Register_8bit is
    Port (
        D   : in STD_LOGIC_VECTOR(7 downto 0);
        ena : in STD_LOGIC;
        clk : in STD_LOGIC;
        rst : in STD_LOGIC;
        Q   : out STD_LOGIC_VECTOR(7 downto 0)
    );
end Register_8bit;

architecture Behavioral of Register_8bit is
    signal Q_reg : STD_LOGIC_VECTOR(7 downto 0);
begin
    process (clk, rst)
    begin
        if rst = '1' then
            Q_reg <= (others => '0');
        elsif rising_edge(clk) then
            if ena = '1' then
                Q_reg <= D;
            end if;
        end if;
    end process;

    Q <= Q_reg;
end Behavioral;