24 lines
590 B
VHDL
24 lines
590 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity Multiplexer_8to1 is
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Port (
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Data_0 : in STD_LOGIC_VECTOR(7 downto 0);
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Data_1 : in STD_LOGIC_VECTOR(7 downto 0);
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Sel : in STD_LOGIC_VECTOR(2 downto 0);
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Y : out STD_LOGIC_VECTOR(7 downto 0)
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);
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end Multiplexer_8to1;
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architecture Behavioral of Multiplexer_8to1 is
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begin
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process(Data_0, Data_1, Sel)
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begin
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case Sel is
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when "000" =>
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Y <= Data_0;
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when others =>
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Y <= Data_1;
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end case;
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end process;
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end Behavioral;
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