54 lines
1.8 KiB
VHDL
54 lines
1.8 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity ALU is
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Port (
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A, B : in STD_LOGIC_VECTOR(7 downto 0); -- Input operands A and B
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ALUOp : in STD_LOGIC_VECTOR(2 downto 0); -- ALU operation code
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ALUSrc : in STD_LOGIC; -- Select between B and an immediate value
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result : out STD_LOGIC_VECTOR(7 downto 0) -- Output result
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);
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end ALU;
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architecture Behavioral of ALU is
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begin
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process (A, B, ALUOp, ALUSrc)
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variable temp_result : STD_LOGIC_VECTOR(7 downto 0);
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begin
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-- Initialize temp_result to zero
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temp_result := (others => '0');
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-- Perform ALU operations based on ALUOp
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case ALUOp is
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when "000" =>
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if ALUSrc = '1' then
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temp_result := A + B; -- ADD operation
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else
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temp_result := A + (others => '1'); -- ADD with immediate value
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end if;
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when "001" =>
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if ALUSrc = '1' then
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temp_result := A - B; -- SUB operation
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else
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temp_result := A - (others => '1'); -- SUB with immediate value
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end if;
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when "010" =>
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temp_result := A AND B; -- AND operation
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when "011" =>
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temp_result := A OR B; -- OR operation
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when "100" =>
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temp_result := A XOR B; -- XOR operation
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when "101" =>
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-- You can add more operations here as needed
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-- temp_result := ...;
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when others =>
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-- Handle undefined or unsupported operations
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temp_result := (others => '0');
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end case;
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result <= temp_result; -- Output the result
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end process;
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end Behavioral;
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