Imbus/xv6-riscv-kernel
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This commit is contained in:
Robert Morris 2022-08-09 14:17:46 -04:00
parent af9abaca05
commit 27a669ef25
4 changed files with 23 additions and 19 deletions
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2
kernel/entry.S
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@ -1,5 +1,5 @@
# qemu -kernel loads the kernel at 0x80000000 # qemu -kernel loads the kernel at 0x80000000
# and causes each CPU to jump there. # and causes each hart (i.e. CPU) to jump there.
# kernel.ld causes the following code to # kernel.ld causes the following code to
# be placed at 0x80000000. # be placed at 0x80000000.
.section .text .section .text

19
kernel/kernelvec.S
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@ -2,16 +2,18 @@
# interrupts and exceptions while in supervisor # interrupts and exceptions while in supervisor
# mode come here. # mode come here.
# #
# push all registers, call kerneltrap(), restore, return. # the current stack is a kernel stack.
# push all registers, call kerneltrap().
# when kerneltrap() returns, restore registers, return.
# #
.globl kerneltrap .globl kerneltrap
.globl kernelvec .globl kernelvec
.align 4 .align 4
kernelvec: kernelvec:
// make room to save registers. # make room to save registers.
addi sp, sp, -256 addi sp, sp, -256
// save the registers. # save the registers.
sd ra, 0(sp) sd ra, 0(sp)
sd sp, 8(sp) sd sp, 8(sp)
sd gp, 16(sp) sd gp, 16(sp)
@ -44,14 +46,14 @@ kernelvec:
sd t5, 232(sp) sd t5, 232(sp)
sd t6, 240(sp) sd t6, 240(sp)
// call the C trap handler in trap.c # call the C trap handler in trap.c
call kerneltrap call kerneltrap
// restore registers. # restore registers.
ld ra, 0(sp) ld ra, 0(sp)
ld sp, 8(sp) ld sp, 8(sp)
ld gp, 16(sp) ld gp, 16(sp)
// not this, in case we moved CPUs: ld tp, 24(sp) # not tp (contains hartid), in case we moved CPUs
ld t0, 32(sp) ld t0, 32(sp)
ld t1, 40(sp) ld t1, 40(sp)
ld t2, 48(sp) ld t2, 48(sp)
@ -82,7 +84,7 @@ kernelvec:
addi sp, sp, 256 addi sp, sp, 256
// return to whatever we were doing in the kernel. # return to whatever we were doing in the kernel.
sret sret
# #
@ -109,7 +111,8 @@ timervec:
add a3, a3, a2 add a3, a3, a2
sd a3, 0(a1) sd a3, 0(a1)
# raise a supervisor software interrupt. # arrange for a supervisor software interrupt
# after this handler returns.
li a1, 2 li a1, 2
csrw sip, a1 csrw sip, a1

4
kernel/riscv.h
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@ -295,7 +295,7 @@ r_sp()
return x; return x;
} }
// read and write tp, the thread pointer, which holds // read and write tp, the thread pointer, which xv6 uses to hold
// this core's hartid (core number), the index into cpus[]. // this core's hartid (core number), the index into cpus[].
static inline uint64 static inline uint64
r_tp() r_tp()
@ -342,7 +342,7 @@ typedef uint64 *pagetable_t; // 512 PTEs
#define PTE_R (1L << 1) #define PTE_R (1L << 1)
#define PTE_W (1L << 2) #define PTE_W (1L << 2)
#define PTE_X (1L << 3) #define PTE_X (1L << 3)
#define PTE_U (1L << 4) // 1 -> user can access #define PTE_U (1L << 4) // user can access
// shift a physical address to the right place for a PTE. // shift a physical address to the right place for a PTE.
#define PA2PTE(pa) ((((uint64)pa) >> 12) << 10) #define PA2PTE(pa) ((((uint64)pa) >> 12) << 10)

5
kernel/start.c
View file

@ -54,8 +54,9 @@ start()
asm volatile("mret"); asm volatile("mret");
} }
// set up to receive timer interrupts in machine mode, // arrange to receive timer interrupts.
// which arrive at timervec in kernelvec.S, // they will arrive in machine mode at
// at timervec in kernelvec.S,
// which turns them into software interrupts for // which turns them into software interrupts for
// devintr() in trap.c. // devintr() in trap.c.
void void