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In-source documentation of sepc and scause instructions

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Imbus 2024-08-09 04:34:11 +02:00
parent 9b339273bb
commit 3e639fe25d
1 changed files with 9 additions and 1 deletions
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10
kernel/riscv.h
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@ -161,9 +161,17 @@ w_mie(u64 x)
asm volatile("csrw mie, %0" : : "r"(x)); asm volatile("csrw mie, %0" : : "r"(x));
} }
// supervisor exception program counter, holds the // The supervisor exception program counter holds the
// instruction address to which a return from // instruction address to which a return from
// exception will go. // exception will go.
//
// It is automatically set when an exception occurs.
// It can also be set with the w_sepc() function.
// (A wrapper for csrw sepc, x)
//
// Information related to the cause of the exception
// will be in the scause register. Readable with the
// r_scause() defined below.
/** Write Supervisor Exception Program Counter */ /** Write Supervisor Exception Program Counter */
static inline void static inline void