Extensive documentation of the architecture specific bits
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1 changed files with 146 additions and 48 deletions
194
kernel/riscv.h
194
kernel/riscv.h
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@ -46,12 +46,25 @@ w_mepc(u64 x)
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// Supervisor Status Register, sstatus
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#define SSTATUS_SPP (1L << 8) // Previous mode, 1=Supervisor, 0=User
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#define SSTATUS_SPIE (1L << 5) // Supervisor Previous Interrupt Enable
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#define SSTATUS_UPIE (1L << 4) // User Previous Interrupt Enable
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#define SSTATUS_SIE (1L << 1) // Supervisor Interrupt Enable
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#define SSTATUS_UIE (1L << 0) // User Interrupt Enable
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/** Supervisor Previous Privilege */
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#define SSTATUS_SPP (1L << 8) // Previous mode, 1=Supervisor, 0=User
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/** Supervisor Previous Interrupt Enable */
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#define SSTATUS_SPIE (1L << 5)
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/** User Previous Interrupt Enable */
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#define SSTATUS_UPIE (1L << 4)
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/** Supervisor Interrupt Enable */
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#define SSTATUS_SIE (1L << 1)
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/** User Interrupt Enable */
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#define SSTATUS_UIE (1L << 0)
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/**
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* Read the value of the sstatus register.
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* (Supervisor Status Register)
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*/
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static inline u64
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r_sstatus()
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{
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@ -60,13 +73,17 @@ r_sstatus()
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return x;
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}
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/**
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* Write a value to the sstatus register.
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* (Supervisor Status Register)
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*/
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static inline void
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w_sstatus(u64 x)
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{
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asm volatile("csrw sstatus, %0" : : "r"(x));
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}
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// Supervisor Interrupt Pending
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/** Read Suporvisor Interrupt Pending */
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static inline u64
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r_sip()
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{
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@ -75,16 +92,26 @@ r_sip()
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return x;
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}
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/** Write Suporvisor Interrupt Pending */
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static inline void
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w_sip(u64 x)
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{
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asm volatile("csrw sip, %0" : : "r"(x));
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}
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// Supervisor Interrupt Enable
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#define SIE_SEIE (1L << 9) // external
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#define SIE_STIE (1L << 5) // timer
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#define SIE_SSIE (1L << 1) // software
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/** Supervisor External Interrup Enable */
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#define SIE_SEIE (1L << 9)
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/** Supervisor Timer Interrupt Enable */
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#define SIE_STIE (1L << 5)
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/** Supervisor Software Interrupt Enable */
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#define SIE_SSIE (1L << 1)
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/**
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* Read the value of the sie register.
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* (Supervisor Interrupt Enable)
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*/
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static inline u64
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r_sie()
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{
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@ -93,16 +120,29 @@ r_sie()
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return x;
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}
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/**
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* Write the valie to the sie rgister
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* (Supervisor Interrupt Enable)
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*/
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static inline void
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w_sie(u64 x)
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{
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asm volatile("csrw sie, %0" : : "r"(x));
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}
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// Machine-mode Interrupt Enable
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#define MIE_MEIE (1L << 11) // external
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#define MIE_MTIE (1L << 7) // timer
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#define MIE_MSIE (1L << 3) // software
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/** Machine External Interrupt Enable */
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#define MIE_MEIE (1L << 11)
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/** Machine Timer Interrupt Enable */
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#define MIE_MTIE (1L << 7)
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/** Machine Software Interrupt Enable */
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#define MIE_MSIE (1L << 3)
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/**
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* Read the value of the mie register.
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* (Machine Interrupt Enable)
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*/
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static inline u64
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r_mie()
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{
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@ -111,6 +151,10 @@ r_mie()
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return x;
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}
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/**
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* Write the value to the mie register.
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* (Machine Interrupt Enable)
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*/
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static inline void
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w_mie(u64 x)
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{
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@ -120,12 +164,15 @@ w_mie(u64 x)
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// supervisor exception program counter, holds the
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// instruction address to which a return from
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// exception will go.
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/** Write Supervisor Exception Program Counter */
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static inline void
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w_sepc(u64 x)
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{
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asm volatile("csrw sepc, %0" : : "r"(x));
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}
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/** Read Supervisor Exception Program Counter */
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static inline u64
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r_sepc()
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{
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@ -134,7 +181,7 @@ r_sepc()
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return x;
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}
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// Machine Exception Delegation
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/** Read Machine Exception Delegation */
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static inline u64
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r_medeleg()
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{
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@ -143,13 +190,14 @@ r_medeleg()
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return x;
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}
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/** Write Machine Exception Delegation */
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static inline void
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w_medeleg(u64 x)
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{
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asm volatile("csrw medeleg, %0" : : "r"(x));
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}
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// Machine Interrupt Delegation
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/** Read Machine Interrupt Delegation */
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static inline u64
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r_mideleg()
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{
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@ -158,20 +206,21 @@ r_mideleg()
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return x;
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}
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/** Write Machine Interrupt Delegation */
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static inline void
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w_mideleg(u64 x)
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{
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asm volatile("csrw mideleg, %0" : : "r"(x));
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}
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// Supervisor Trap-Vector Base Address
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// low two bits are mode.
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/** Write Supervisor Trap-Vector Base Address */
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static inline void
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w_stvec(u64 x)
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{
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asm volatile("csrw stvec, %0" : : "r"(x));
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}
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/** Read Supervisor Trap-Vector Base Address */
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static inline u64
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r_stvec()
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{
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@ -180,39 +229,50 @@ r_stvec()
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return x;
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}
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// Machine-mode interrupt vector
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/** Write Machine Trap-Vector Base Address */
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static inline void
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w_mtvec(u64 x)
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{
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asm volatile("csrw mtvec, %0" : : "r"(x));
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}
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// Physical Memory Protection
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/** Read Physical Memory Protection Configuration */
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static inline void
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w_pmpcfg0(u64 x)
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{
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asm volatile("csrw pmpcfg0, %0" : : "r"(x));
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}
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/** Write Physical Memory Protection Configuration */
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static inline void
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w_pmpaddr0(u64 x)
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{
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asm volatile("csrw pmpaddr0, %0" : : "r"(x));
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}
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// use riscv's sv39 page table scheme.
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/** Risc-v's sv39 page table scheme. */
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#define SATP_SV39 (8L << 60)
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/** Make Supervisor Address Translation and Protection */
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#define MAKE_SATP(pagetable) (SATP_SV39 | (((u64)pagetable) >> 12))
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// supervisor address translation and protection;
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// holds the address of the page table.
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/**
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* Write the value to the satp register.
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* (Supervisor Address Translation and Protection)
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*
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* This register holds the address of the page table.
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*/
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static inline void
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w_satp(u64 x)
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{
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asm volatile("csrw satp, %0" : : "r"(x));
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}
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/**
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* Read the value of the satp register.
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* (Supervisor Address Translation and Protection)
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* Returns the address of the page table.
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*/
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static inline u64
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r_satp()
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{
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@ -221,13 +281,14 @@ r_satp()
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return x;
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}
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/** Read Supervisor Scratch Register */
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static inline void
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w_mscratch(u64 x)
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{
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asm volatile("csrw mscratch, %0" : : "r"(x));
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}
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// Supervisor Trap Cause
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/** Supervisor Trap Cause */
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static inline u64
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r_scause()
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{
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@ -236,7 +297,7 @@ r_scause()
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return x;
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}
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// Supervisor Trap Value
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/** Supervisor Trap Value */
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static inline u64
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r_stval()
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{
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@ -245,13 +306,14 @@ r_stval()
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return x;
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}
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// Machine-mode Counter-Enable
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/** Write Machine-mode Counter-Enable Register */
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static inline void
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w_mcounteren(u64 x)
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{
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asm volatile("csrw mcounteren, %0" : : "r"(x));
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}
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/** Read Machine-mode Counter-Enable Register */
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static inline u64
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r_mcounteren()
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{
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@ -260,7 +322,10 @@ r_mcounteren()
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return x;
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}
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// machine-mode cycle counter
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/**
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* Machine-mode cycle counter
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* Reports the current wall-clock time from the timer device.
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*/
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static inline u64
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r_time()
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{
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@ -269,21 +334,21 @@ r_time()
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return x;
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}
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// enable device interrupts
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/** Enable device interrupts */
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static inline void
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intr_on()
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{
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w_sstatus(r_sstatus() | SSTATUS_SIE);
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}
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// disable device interrupts
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/** Disable device interrupts */
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static inline void
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intr_off()
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{
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w_sstatus(r_sstatus() & ~SSTATUS_SIE);
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}
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// are device interrupts enabled?
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/** Are device interrupts enabled? */
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static inline int
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intr_get()
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{
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@ -291,6 +356,7 @@ intr_get()
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return (x & SSTATUS_SIE) != 0;
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}
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/** Read stack pointer */
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static inline u64
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r_sp()
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{
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@ -301,6 +367,8 @@ r_sp()
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// read and write tp, the thread pointer, which xv6 uses to hold
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// this core's hartid (core number), the index into cpus[].
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/** Read thread pointer */
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static inline u64
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r_tp()
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{
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@ -309,12 +377,14 @@ r_tp()
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return x;
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}
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/** Write thread pointer */
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static inline void
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w_tp(u64 x)
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{
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asm volatile("mv tp, %0" : : "r"(x));
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}
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/** Read the return address */
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static inline u64
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r_ra()
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{
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@ -323,7 +393,7 @@ r_ra()
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return x;
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}
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// flush the TLB.
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/** Flush the TLB (Translation Lookaside Buffer) */
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static inline void
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sfence_vma()
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{
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@ -331,37 +401,65 @@ sfence_vma()
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asm volatile("sfence.vma zero, zero");
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}
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typedef u64 pte_t;
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/** Page Table Entry Type */
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typedef u64 pte_t;
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/** Page Table Type */
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typedef u64 *pagetable_t; // 512 PTEs
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#endif // __ASSEMBLER__
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#define PGSIZE 4096 // bytes per page
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#define PGSHIFT 12 // bits of offset within a page
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/** Page Size */
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#define PGSIZE 4096 // bytes per page
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/** Page Shift, bits of offset within a page */
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#define PGSHIFT 12
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#define PGROUNDUP(sz) (((sz) + PGSIZE - 1) & ~(PGSIZE - 1))
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#define PGROUNDDOWN(a) (((a)) & ~(PGSIZE - 1))
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#define PTE_V (1L << 0) // valid
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#define PTE_R (1L << 1)
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#define PTE_W (1L << 2)
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#define PTE_X (1L << 3)
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#define PTE_U (1L << 4) // user can access
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/**
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* Page Table Entry Flags
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*/
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// shift a physical address to the right place for a PTE.
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#define PTE_V (1L << 0) /** PTE Valid */
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#define PTE_R (1L << 1) /** PTE Readable */
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#define PTE_W (1L << 2) /** PTE Writeable */
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#define PTE_X (1L << 3) /** PTE Executable */
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#define PTE_U (1L << 4) /** PTE User Accessible */
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/**
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* Helper macros to shift a physical address
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* to the right place for a PTE.
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*/
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/** Physical Address to Page Table Entry */
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#define PA2PTE(pa) ((((u64)pa) >> 12) << 10)
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/** Page Table Entry to Physical Address */
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#define PTE2PA(pte) (((pte) >> 10) << 12)
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/** Page Table Entry Flags */
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#define PTE_FLAGS(pte) ((pte) & 0x3FF)
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// extract the three 9-bit page table indices from a virtual address.
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#define PXMASK 0x1FF // 9 bits
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#define PXSHIFT(level) (PGSHIFT + (9 * (level)))
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#define PX(level, va) ((((u64)(va)) >> PXSHIFT(level)) & PXMASK)
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/**
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* Helper macros to extract the three 9-bit
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* page table indices from a virtual address.
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*/
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// one beyond the highest possible virtual address.
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// MAXVA is actually one bit less than the max allowed by
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// Sv39, to avoid having to sign-extend virtual addresses
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// that have the high bit set.
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/** Page Extract Mask */
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#define PXMASK 0x1FF // 9 bits, 0b111111111
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/** Page Extract Shift */
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#define PXSHIFT(level) (PGSHIFT + (9 * (level)))
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/** Page Extract */
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#define PX(level, va) ((((u64)(va)) >> PXSHIFT(level)) & PXMASK)
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/**
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* One beyond the highest possible virtual address.
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* MAXVA is actually one bit less than the max allowed by
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* Sv39, to avoid having to sign-extend virtual addresses
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* that have the high bit set.
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*/
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#define MAXVA (1L << (9 + 9 + 9 + 12 - 1))
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