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Imbus 2024-08-07 14:33:58 +02:00
parent 5bbe3619df
commit 5829a06e3a
1 changed files with 23 additions and 23 deletions
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46
kernel/start.c
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@ -6,69 +6,69 @@
void main();
void timerinit();
// entry.S needs one stack per CPU.
// Entry.S needs one stack per CPU.
__attribute__((aligned(16))) char stack0[4096 * NCPU];
// a scratch area per CPU for machine-mode timer interrupts.
// A scratch area per CPU for machine-mode timer interrupts.
u64 timer_scratch[NCPU][5];
// assembly code in kernelvec.S for machine-mode timer interrupt.
// Assembly code in kernelvec.S for machine-mode timer interrupt.
extern void timervec();
// entry.S jumps here in machine mode on stack0.
// Entry.S jumps here in machine mode on stack0.
void
start()
{
// set M Previous Privilege mode to Supervisor, for mret.
// Set M Previous Privilege mode to Supervisor, for mret.
unsigned long x = r_mstatus();
x &= ~MSTATUS_MPP_MASK;
x |= MSTATUS_MPP_S;
w_mstatus(x);
// set M Exception Program Counter to main, for mret.
// requires gcc -mcmodel=medany
// Set M Exception Program Counter to main, for mret.
// Requires gcc -mcmodel=medany
w_mepc((u64)main);
// disable paging for now.
// Disable paging for now.
w_satp(0);
// delegate all interrupts and exceptions to supervisor mode.
// Delegate all interrupts and exceptions to supervisor mode.
w_medeleg(0xffff);
w_mideleg(0xffff);
w_sie(r_sie() | SIE_SEIE | SIE_STIE | SIE_SSIE);
// configure Physical Memory Protection to give supervisor mode
// access to all of physical memory.
// Configure Physical Memory Protection to give supervisor mode
// Access to all of physical memory.
w_pmpaddr0(0x3fffffffffffffull);
w_pmpcfg0(0xf);
// ask for clock interrupts.
// Ask for clock interrupts.
timerinit();
// keep each CPU's hartid in its tp register, for cpuid().
// Keep each CPU's hartid in its tp register, for cpuid().
int id = r_mhartid();
w_tp(id);
// switch to supervisor mode and jump to main().
// Switch to supervisor mode and jump to main().
asm volatile("mret");
}
// arrange to receive timer interrupts.
// they will arrive in machine mode at
// Arrange to receive timer interrupts.
// They will arrive in machine mode at
// at timervec in kernelvec.S,
// which turns them into software interrupts for
// devintr() in trap.c.
void
timerinit()
{
// each CPU has a separate source of timer interrupts.
// Each CPU has a separate source of timer interrupts.
int id = r_mhartid();
// ask the CLINT for a timer interrupt.
int interval = 1000000; // cycles; about 1/10th second in qemu.
// Ask the CLINT for a timer interrupt.
int interval = 1000000; // Cycles; about 1/10th second in qemu.
*(u64 *)CLINT_MTIMECMP(id) = *(u64 *)CLINT_MTIME + interval;
// prepare information in scratch[] for timervec.
// Prepare information in scratch[] for timervec.
// scratch[0..2] : space for timervec to save registers.
// scratch[3] : address of CLINT MTIMECMP register.
// scratch[4] : desired interval (in cycles) between timer interrupts.
@ -77,12 +77,12 @@ timerinit()
scratch[4] = interval;
w_mscratch((u64)scratch);
// set the machine-mode trap handler.
// Set the machine-mode trap handler.
w_mtvec((u64)timervec);
// enable machine-mode interrupts.
// Enable machine-mode interrupts.
w_mstatus(r_mstatus() | MSTATUS_MIE);
// enable machine-mode timer interrupts.
// Enable machine-mode timer interrupts.
w_mie(r_mie() | MIE_MTIE);
}