Complete reformat
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Imbus
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d6793bf093
60 changed files with 1952 additions and 1995 deletions
130
kernel/riscv.h
130
kernel/riscv.h
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@ -5,61 +5,61 @@ static inline u64
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r_mhartid()
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{
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u64 x;
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asm volatile("csrr %0, mhartid" : "=r" (x) );
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asm volatile("csrr %0, mhartid" : "=r"(x));
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return x;
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}
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// Machine Status Register, mstatus
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#define MSTATUS_MPP_MASK (3L << 11) // previous mode.
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#define MSTATUS_MPP_M (3L << 11)
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#define MSTATUS_MPP_S (1L << 11)
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#define MSTATUS_MPP_U (0L << 11)
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#define MSTATUS_MIE (1L << 3) // machine-mode interrupt enable.
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#define MSTATUS_MPP_M (3L << 11)
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#define MSTATUS_MPP_S (1L << 11)
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#define MSTATUS_MPP_U (0L << 11)
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#define MSTATUS_MIE (1L << 3) // machine-mode interrupt enable.
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static inline u64
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r_mstatus()
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{
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u64 x;
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asm volatile("csrr %0, mstatus" : "=r" (x) );
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asm volatile("csrr %0, mstatus" : "=r"(x));
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return x;
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}
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static inline void
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static inline void
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w_mstatus(u64 x)
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{
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asm volatile("csrw mstatus, %0" : : "r" (x));
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asm volatile("csrw mstatus, %0" : : "r"(x));
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}
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// machine exception program counter, holds the
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// instruction address to which a return from
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// exception will go.
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static inline void
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static inline void
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w_mepc(u64 x)
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{
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asm volatile("csrw mepc, %0" : : "r" (x));
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asm volatile("csrw mepc, %0" : : "r"(x));
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}
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// Supervisor Status Register, sstatus
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#define SSTATUS_SPP (1L << 8) // Previous mode, 1=Supervisor, 0=User
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#define SSTATUS_SPP (1L << 8) // Previous mode, 1=Supervisor, 0=User
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#define SSTATUS_SPIE (1L << 5) // Supervisor Previous Interrupt Enable
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#define SSTATUS_UPIE (1L << 4) // User Previous Interrupt Enable
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#define SSTATUS_SIE (1L << 1) // Supervisor Interrupt Enable
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#define SSTATUS_UIE (1L << 0) // User Interrupt Enable
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#define SSTATUS_SIE (1L << 1) // Supervisor Interrupt Enable
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#define SSTATUS_UIE (1L << 0) // User Interrupt Enable
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static inline u64
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r_sstatus()
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{
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u64 x;
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asm volatile("csrr %0, sstatus" : "=r" (x) );
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asm volatile("csrr %0, sstatus" : "=r"(x));
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return x;
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}
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static inline void
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static inline void
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w_sstatus(u64 x)
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{
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asm volatile("csrw sstatus, %0" : : "r" (x));
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asm volatile("csrw sstatus, %0" : : "r"(x));
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}
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// Supervisor Interrupt Pending
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@ -67,14 +67,14 @@ static inline u64
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r_sip()
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{
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u64 x;
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asm volatile("csrr %0, sip" : "=r" (x) );
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asm volatile("csrr %0, sip" : "=r"(x));
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return x;
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}
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static inline void
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static inline void
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w_sip(u64 x)
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{
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asm volatile("csrw sip, %0" : : "r" (x));
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asm volatile("csrw sip, %0" : : "r"(x));
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}
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// Supervisor Interrupt Enable
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@ -85,14 +85,14 @@ static inline u64
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r_sie()
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{
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u64 x;
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asm volatile("csrr %0, sie" : "=r" (x) );
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asm volatile("csrr %0, sie" : "=r"(x));
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return x;
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}
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static inline void
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static inline void
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w_sie(u64 x)
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{
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asm volatile("csrw sie, %0" : : "r" (x));
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asm volatile("csrw sie, %0" : : "r"(x));
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}
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// Machine-mode Interrupt Enable
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@ -103,30 +103,30 @@ static inline u64
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r_mie()
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{
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u64 x;
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asm volatile("csrr %0, mie" : "=r" (x) );
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asm volatile("csrr %0, mie" : "=r"(x));
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return x;
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}
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static inline void
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static inline void
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w_mie(u64 x)
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{
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asm volatile("csrw mie, %0" : : "r" (x));
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asm volatile("csrw mie, %0" : : "r"(x));
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}
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// supervisor exception program counter, holds the
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// instruction address to which a return from
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// exception will go.
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static inline void
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static inline void
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w_sepc(u64 x)
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{
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asm volatile("csrw sepc, %0" : : "r" (x));
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asm volatile("csrw sepc, %0" : : "r"(x));
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}
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static inline u64
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r_sepc()
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{
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u64 x;
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asm volatile("csrr %0, sepc" : "=r" (x) );
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asm volatile("csrr %0, sepc" : "=r"(x));
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return x;
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}
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@ -135,14 +135,14 @@ static inline u64
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r_medeleg()
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{
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u64 x;
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asm volatile("csrr %0, medeleg" : "=r" (x) );
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asm volatile("csrr %0, medeleg" : "=r"(x));
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return x;
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}
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static inline void
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static inline void
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w_medeleg(u64 x)
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{
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asm volatile("csrw medeleg, %0" : : "r" (x));
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asm volatile("csrw medeleg, %0" : : "r"(x));
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}
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// Machine Interrupt Delegation
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@ -150,50 +150,50 @@ static inline u64
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r_mideleg()
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{
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u64 x;
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asm volatile("csrr %0, mideleg" : "=r" (x) );
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asm volatile("csrr %0, mideleg" : "=r"(x));
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return x;
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}
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static inline void
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static inline void
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w_mideleg(u64 x)
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{
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asm volatile("csrw mideleg, %0" : : "r" (x));
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asm volatile("csrw mideleg, %0" : : "r"(x));
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}
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// Supervisor Trap-Vector Base Address
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// low two bits are mode.
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static inline void
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static inline void
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w_stvec(u64 x)
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{
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asm volatile("csrw stvec, %0" : : "r" (x));
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asm volatile("csrw stvec, %0" : : "r"(x));
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}
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static inline u64
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r_stvec()
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{
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u64 x;
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asm volatile("csrr %0, stvec" : "=r" (x) );
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asm volatile("csrr %0, stvec" : "=r"(x));
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return x;
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}
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// Machine-mode interrupt vector
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static inline void
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static inline void
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w_mtvec(u64 x)
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{
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asm volatile("csrw mtvec, %0" : : "r" (x));
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asm volatile("csrw mtvec, %0" : : "r"(x));
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}
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// Physical Memory Protection
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static inline void
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w_pmpcfg0(u64 x)
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{
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asm volatile("csrw pmpcfg0, %0" : : "r" (x));
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asm volatile("csrw pmpcfg0, %0" : : "r"(x));
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}
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static inline void
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w_pmpaddr0(u64 x)
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{
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asm volatile("csrw pmpaddr0, %0" : : "r" (x));
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asm volatile("csrw pmpaddr0, %0" : : "r"(x));
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}
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// use riscv's sv39 page table scheme.
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@ -203,24 +203,24 @@ w_pmpaddr0(u64 x)
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// supervisor address translation and protection;
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// holds the address of the page table.
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static inline void
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static inline void
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w_satp(u64 x)
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{
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asm volatile("csrw satp, %0" : : "r" (x));
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asm volatile("csrw satp, %0" : : "r"(x));
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}
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static inline u64
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r_satp()
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{
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u64 x;
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asm volatile("csrr %0, satp" : "=r" (x) );
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asm volatile("csrr %0, satp" : "=r"(x));
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return x;
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}
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static inline void
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static inline void
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w_mscratch(u64 x)
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{
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asm volatile("csrw mscratch, %0" : : "r" (x));
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asm volatile("csrw mscratch, %0" : : "r"(x));
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}
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// Supervisor Trap Cause
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@ -228,7 +228,7 @@ static inline u64
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r_scause()
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{
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u64 x;
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asm volatile("csrr %0, scause" : "=r" (x) );
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asm volatile("csrr %0, scause" : "=r"(x));
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return x;
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}
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@ -237,22 +237,22 @@ static inline u64
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r_stval()
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{
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u64 x;
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asm volatile("csrr %0, stval" : "=r" (x) );
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asm volatile("csrr %0, stval" : "=r"(x));
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return x;
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}
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// Machine-mode Counter-Enable
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static inline void
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static inline void
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w_mcounteren(u64 x)
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{
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asm volatile("csrw mcounteren, %0" : : "r" (x));
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asm volatile("csrw mcounteren, %0" : : "r"(x));
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}
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static inline u64
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r_mcounteren()
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{
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u64 x;
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asm volatile("csrr %0, mcounteren" : "=r" (x) );
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asm volatile("csrr %0, mcounteren" : "=r"(x));
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return x;
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}
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@ -261,7 +261,7 @@ static inline u64
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r_time()
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{
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u64 x;
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asm volatile("csrr %0, time" : "=r" (x) );
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asm volatile("csrr %0, time" : "=r"(x));
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return x;
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}
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@ -291,7 +291,7 @@ static inline u64
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r_sp()
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{
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u64 x;
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asm volatile("mv %0, sp" : "=r" (x) );
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asm volatile("mv %0, sp" : "=r"(x));
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return x;
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}
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@ -301,21 +301,21 @@ static inline u64
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r_tp()
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{
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u64 x;
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asm volatile("mv %0, tp" : "=r" (x) );
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asm volatile("mv %0, tp" : "=r"(x));
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return x;
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}
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static inline void
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static inline void
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w_tp(u64 x)
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{
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asm volatile("mv tp, %0" : : "r" (x));
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asm volatile("mv tp, %0" : : "r"(x));
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}
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static inline u64
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r_ra()
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{
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u64 x;
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asm volatile("mv %0, ra" : "=r" (x) );
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asm volatile("mv %0, ra" : "=r"(x));
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return x;
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}
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@ -327,16 +327,16 @@ sfence_vma()
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asm volatile("sfence.vma zero, zero");
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}
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typedef u64 pte_t;
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typedef u64 pte_t;
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typedef u64 *pagetable_t; // 512 PTEs
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#endif // __ASSEMBLER__
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#define PGSIZE 4096 // bytes per page
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#define PGSHIFT 12 // bits of offset within a page
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#define PGSIZE 4096 // bytes per page
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#define PGSHIFT 12 // bits of offset within a page
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#define PGROUNDUP(sz) (((sz)+PGSIZE-1) & ~(PGSIZE-1))
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#define PGROUNDDOWN(a) (((a)) & ~(PGSIZE-1))
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#define PGROUNDUP(sz) (((sz) + PGSIZE - 1) & ~(PGSIZE - 1))
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#define PGROUNDDOWN(a) (((a)) & ~(PGSIZE - 1))
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#define PTE_V (1L << 0) // valid
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#define PTE_R (1L << 1)
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@ -352,9 +352,9 @@ typedef u64 *pagetable_t; // 512 PTEs
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#define PTE_FLAGS(pte) ((pte) & 0x3FF)
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// extract the three 9-bit page table indices from a virtual address.
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#define PXMASK 0x1FF // 9 bits
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#define PXSHIFT(level) (PGSHIFT+(9*(level)))
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#define PX(level, va) ((((u64) (va)) >> PXSHIFT(level)) & PXMASK)
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#define PXMASK 0x1FF // 9 bits
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#define PXSHIFT(level) (PGSHIFT + (9 * (level)))
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#define PX(level, va) ((((u64)(va)) >> PXSHIFT(level)) & PXMASK)
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// one beyond the highest possible virtual address.
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// MAXVA is actually one bit less than the max allowed by
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