diff --git a/kernel/riscv.h b/kernel/riscv.h
index 47d5397..f0db6c8 100644
--- a/kernel/riscv.h
+++ b/kernel/riscv.h
@@ -21,6 +21,16 @@ r_mhartid()
 #define MSTATUS_MPP_U    (0L << 11)
 #define MSTATUS_MIE      (1L << 3) // machine-mode interrupt enable.
 
+#define MTVEC_MODE_DIRECT   0x0 // mtvec MODE values (RISC-V Privileged Spec)
+#define MTVEC_MODE_VECTORED 0x1
+#define MTVEC_MODE_MASK     0x3 // Mask for the MODE bits (bits [1:0])
+
+// Align an mtvec base address (clear low 2 bits)
+#define MTVEC_ALIGN(addr) ((uintptr_t)(addr) & ~MTVEC_MODE_MASK)
+
+// Construct a complete mtvec value from BASE + MODE
+#define MTVEC_VALUE(base, mode) (MTVEC_ALIGN(base) | ((mode) & MTVEC_MODE_MASK))
+
 static inline u64
 r_mstatus()
 {
diff --git a/kernel/start.c b/kernel/start.c
index fa199be..a438556 100644
--- a/kernel/start.c
+++ b/kernel/start.c
@@ -77,8 +77,8 @@ timerinit()
   scratch[4] = interval;
   w_mscratch((u64)scratch);
 
-  // Set the machine-mode trap handler.
-  w_mtvec((u64)timervec);
+  // Set the machine-mode trap handler. Set to direct, since scause is examined in the handler.
+  w_mtvec(MTVEC_VALUE((u64)timervec, MTVEC_MODE_DIRECT));
 
   // Enable machine-mode interrupts.
   w_mstatus(r_mstatus() | MSTATUS_MIE);