Imbus/xv6-riscv-kernel
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run without lapic and ioapic, if they are not present

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if no lapic available, use 8253pit for clock
now xv6 runs both on qemu (uniprocessor) and bochs (uniprocessor and MP)
This commit is contained in:
kaashoek 2006-09-07 01:37:58 +00:00
parent f9bc4452b5
commit f70172129c
12 changed files with 128 additions and 48 deletions
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66
ioapic.c
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@ -37,28 +37,30 @@ ioapic_init(void)
uchar id;
int i;
io = (struct ioapic*) IO_APIC_BASE;
l = ioapic_read(io, IOAPIC_VER);
nintr = ((l & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1;
id = ioapic_read(io, IOAPIC_ID) >> APIC_ID_SHIFT;
if(id != ioapic_id)
panic("ioapic_init: id isn't equal to ioapic_id\n");
for(i = 0; i < nintr; i++) {
// active-hi and edge-triggered for ISA interrupts
// Assume that pin 0 on the first I/O APIC is an ExtINT pin.
// Assume that pins 1-15 are ISA interrupts
l = ioapic_read(io, IOAPIC_REDTBL_LO(i));
l = l & ~IOART_INTMASK; // allow INTs
l |= IOART_INTMSET;
l = l & ~IOART_INTPOL; // active hi
l = l & ~IOART_TRGRMOD; // edgee triggered
l = l & ~IOART_DELMOD; // fixed
l = l & ~IOART_DESTMOD; // physical mode
l = l | (IRQ_OFFSET + i); // vector
ioapic_write(io, IOAPIC_REDTBL_LO(i), l);
h = ioapic_read(io, IOAPIC_REDTBL_HI(i));
h &= ~IOART_DEST;
ioapic_write(io, IOAPIC_REDTBL_HI(i), h);
if (ismp) {
io = (struct ioapic*) IO_APIC_BASE;
l = ioapic_read(io, IOAPIC_VER);
nintr = ((l & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1;
id = ioapic_read(io, IOAPIC_ID) >> APIC_ID_SHIFT;
if(id != ioapic_id)
cprintf("ioapic_init: id isn't equal to ioapic_id; not a MP\n");
for(i = 0; i < nintr; i++) {
// active-hi and edge-triggered for ISA interrupts
// Assume that pin 0 on the first I/O APIC is an ExtINT pin.
// Assume that pins 1-15 are ISA interrupts
l = ioapic_read(io, IOAPIC_REDTBL_LO(i));
l = l & ~IOART_INTMASK; // allow INTs
l |= IOART_INTMSET;
l = l & ~IOART_INTPOL; // active hi
l = l & ~IOART_TRGRMOD; // edgee triggered
l = l & ~IOART_DELMOD; // fixed
l = l & ~IOART_DESTMOD; // physical mode
l = l | (IRQ_OFFSET + i); // vector
ioapic_write(io, IOAPIC_REDTBL_LO(i), l);
h = ioapic_read(io, IOAPIC_REDTBL_HI(i));
h &= ~IOART_DEST;
ioapic_write(io, IOAPIC_REDTBL_HI(i), h);
}
}
}
@ -67,13 +69,15 @@ ioapic_enable (int irq, int cpunum)
{
uint l, h;
struct ioapic *io;
io = (struct ioapic*) IO_APIC_BASE;
l = ioapic_read(io, IOAPIC_REDTBL_LO(irq));
l = l & ~IOART_INTMASK; // allow INTs
ioapic_write(io, IOAPIC_REDTBL_LO(irq), l);
h = ioapic_read(io, IOAPIC_REDTBL_HI(irq));
h &= ~IOART_DEST;
h |= (cpunum << APIC_ID_SHIFT);
ioapic_write(io, IOAPIC_REDTBL_HI(irq), h);
if (ismp) {
io = (struct ioapic*) IO_APIC_BASE;
l = ioapic_read(io, IOAPIC_REDTBL_LO(irq));
l = l & ~IOART_INTMASK; // allow INTs
ioapic_write(io, IOAPIC_REDTBL_LO(irq), l);
h = ioapic_read(io, IOAPIC_REDTBL_HI(irq));
h &= ~IOART_DEST;
h |= (cpunum << APIC_ID_SHIFT);
ioapic_write(io, IOAPIC_REDTBL_HI(irq), h);
}
}