Imbus/xv6-riscv-kernel
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1310 commits 1 branch 0 tags 18 MiB
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10 commits

Author SHA1 Message Date
Matt Harvey
b9359c3533 Corrects order of UART RX/TX interrupt enable bits 
(per http://byterunner.com/16550.html and manually tested in qemu bare metal echo)
 2020-10-03 16:35:47 -04:00
Robert Morris
ffb2ee074a move panicked check to uart.c 2020-08-28 05:51:48 -04:00
Robert Morris
050a69610a defines for UART register bits 2020-07-23 06:27:20 -04:00
Robert Morris
db0f092ae4 fix printf() in interrupts 2020-07-22 10:31:46 -04:00
Robert Morris
823864099d interrupt-driven uart output, hopefully a nice example for teaching. 2020-07-20 06:59:26 -04:00
Robert Morris
1ec50c5848 xxx 2019-07-28 07:43:22 -04:00
Robert Morris
629faafa36 cleaner UART register interface 2019-07-27 06:44:24 -04:00
Robert Morris
a33f60fea3 console/uart tweaks 2019-07-27 05:47:19 -04:00
Frans Kaashoek
67702cf706 Checkpoint switching to per-process locks, in attempt clarify xv6's 
locking plan, which is a difficult to understand because ptable lock
protects many invariants.  This implementation has a bug: once in a
while xv6 unlocks a proc lock that is locked by another core.
 2019-07-02 09:14:47 -04:00
Robert Morris
5753553213 separate source into kernel/ user/ mkfs/ 2019-06-11 09:57:14 -04:00
Renamed from uart.c (Browse further)